| Electronic Components Datasheet Search |
|
ADV7173KST Datasheet(PDF) 17 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADV7173KST Datasheet(HTML) 17 Page - Analog Devices |
|
17 / 59 page ![]() ADV7172/ADV7173 –17– REV. A Mode 0 (CCIR–656): Master Option (Timing Register 0 TR0 = X X X X X 0 0 1) The ADV7172/ADV7173 generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the FIELD/ VSYNC pin. Mode 0 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). The H, V and F transitions relative to the video waveform are illustrated in Figure 26. 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 DISPLAY DISPLAY VERTICAL BLANK ODD FIELD EVEN FIELD H V F 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 ODD FIELD EVEN FIELD DISPLAY DISPLAY VERTICAL BLANK H V F Figure 24. Timing Mode 0 (NTSC Master Mode) 622 623 624 625 1 2 3 4 5 67 21 22 23 DISPLAY DISPLAY VERTICAL BLANK H V F ODD FIELD EVEN FIELD 309 310 311 312 314 315 316 317 318 319 320 334 335 336 DISPLAY DISPLAY VERTICAL BLANK H V F ODD FIELD EVEN FIELD 313 Figure 25. Timing Mode 0 (PAL Master Mode) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |