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RT7232 Datasheet(PDF) 4 Page - Richtek Technology Corporation |
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RT7232 Datasheet(HTML) 4 Page - Richtek Technology Corporation |
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4 / 18 page ![]() RT7231/32/33/34 4 DS7231/32/33/34-00 March 2013 www.richtek.com © Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Function Block Diagram * : VCC pin for TSSOP-14 (Exposed Pad) only. VS pin for TSSOP-14 (Exposed Pad) only. GND pin for TSSOP-14 (Exposed Pad) only. PGOOD pin for TSSOP-14 (Exposed Pad) and WDFN-10L 3x3 only. Operation The RT7231/32/33/34 is a synchronous step-down converter with advanced constant on-time control mode. Using the ACOTTM control mode can reduce the output capacitance and provide fast transient response. It can minimize the component size without additional external compensation network. Power Good (for TSSOP-14 (Exposed Pad) and WDFN-10L 3x3 only) After soft-start is finished, the power good function will be activated. When the FB is activated, the PGOOD will become an open-drain output. If the FB is below, the PGOOD pin will be pulled low. Internal Regulator The regulator provides 5V power to supply the internal control circuit. Connecting a 1 μF ceramic capacitor for decoupling and stability is required. Soft-Start In order to prevent the converter output voltage from overshooting during the startup period, the soft-start function is necessary. The soft-start time is adjustable and can be set by an external capacitor. Current Protection The inductor current is monitored via the internal switches in cycle-by-cycle. Once the output voltage drops under UV threshold, the device will enter latch mode for TSSOP- 14 (Exposed Pad), and hiccup mode for WDFN-10L 3x3. UVLO Protection To protect the chip from operating at insufficient supply voltage, the UVLO is needed. When the input voltage of VCC is lower than the UVLO falling threshold voltage, the device will be latch-off. Output Discharge Control (for TSSOP-14 (Exposed Pad) only) When EN pin is low, the RT7231/32 will discharge the output with an internal 50 Ω MOSFET connected between VOUT to GND pin. Thermal Shutdown When the junction temperature exceeds the OTP threshold value, the IC will shut down the switching operation. Once the junction temperature cools down and is lower than the OTP lower threshold, the converter will automatically resume switching VCC* POR & Reg Driver BOOT VREG5 Control VBIAS On-Time VIN FB Min. Off-Time Ripple Gen. VREF ZC Comparator SS SW PGND EN VREG5 OC + - - 2µA VREG5 UV & OV SW FB VS* VIN Comparator + - FB 0.9 x VREF PGOOD* GND* |
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