RT8073 datasheet(13/16 Pages) RICHTEK

13 / 16 page

RT8073

DS8073-01

November 2012

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Layout Considerations

Follow the PCB layout guidelines for optimal performance

of RT8073.

A ground plane is recommended. If a ground plane layer

is not used, the signal and power grounds should be

segregated with all small-signal components returning

to the GND pin at one point that is then connected to

the PGND pin close to the IC. The exposed pad should

be connected to GND.

Connect the terminal of the input capacitor(s), CIN, as

close as possible to the VIN pin. This capacitor provides

the AC current into the internal power MOSFETs.

LX node is with high frequency voltage swing and should

be kept within small area. Keep all sensitive small-signal

nodes away from the LX node to prevent stray capacitive

noise pick-up.

Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise

of power components.

Connect the FB pin directly to the feedback resistors.

The resistor divider must be connected between VOUT

and GND.

Figure 6. Derating Curve of Maximum Power Dissipation

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TAis

the ambient temperature, and

θJAis the junction to ambient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

θJA, is layout dependent. For

SOP-8 (Exposed Pad) packages, the thermal resistance,

θJA, is 49°C/W on a standard JEDEC 51-7 four-layer

thermal test board. For WDFN-12L 3x3 packages, the

thermal resistance,

θJA, is 60°C/W on a standard JEDEC

51-7 four-layer thermal test board. The maximum power

dissipation at TA = 25

°C can be calculated by the following

formulas :

PD(MAX) = (125

°C − 25°C) / (49°C/W) = 2.041W for

SOP-8 (Exposed Pad) package

PD(MAX) = (125

°C − 25°C) / (60°C/W) = 1.667W for

WDFN-12L 3x3 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. The derating curves in Figure 6 allow the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

100

125

Ambient Temperature (°C)

WDFN-12L 3x3

Four-Layer PCB

SOP-8 (Exposed Pad)

RT8073 Datasheet(PDF) 13 Page - Richtek Technology Corporation

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