DAC8222FS datasheet(4/15 Pages) AD

4 / 15 page

DAC8222

–4–

REV. C

11. AGND

13. DB4

12. IOUT A

14. DB3

13. RFB A

15. DB2

14. VREF A

16. DB1

15. DGND

17. DB0 (LSB)

16. DB11(MSB)

18.

DAC A/DAC B

17. DB10

19.

LDAC

18. DB9

20.

19. DB8

21. VDD

10. DB7

22. VREF B

11. DB6

23. RFB B

12. DB5

24. IOUT B

Substrate (die backside) is internally connected to VDD.

DICE CHARACTERISTICS

DIE SIZE 0.124

× 0.132 inch, 16,368 sq. mils

(3.15

× 3.55 mm, 10.56 sq. mm)

WAFER TEST LIMITS (@ V

DD = +5 V or +15 V, VREF A = VREF B = +10 V, VOUT A = VOUT B = 0 V; AGND = DGND = 0 V; TA = +25 C)

DAC8222G

Parameter

Symbol

Conditions

Limit

Units

Relative Accuracy

INL

Endpoint Linearity Error

±1LSB max

Differential Nonlinearity

DNL

All Grades are Guaranteed Monotonic

±1LSB max

Full Scale Gain Error

GFSE

Digital Inputs = 1111 1111 1111

±4LSB max

Output Leakage

Digital Inputs = 0000 0000 0000

±50

nA max

(IOUT A, IOUT B)ILKG

Pads 2 and 24

Input Resistance

(VREF A, VREF B)RREF

Pads 4 and 22

8/15

Ω max

Input Resistance Match

∆RREF

±1% max

RREF

Digital Input High

VINH

VDD = +5 V

2.4

V min

VDD = +15 V

13.5

V min

Digital Input Low

VINL

VDD = +5 V

0.8

V max

VDD = +15 V

1.5

V min

Digital Input Current

IIN

VIN = 0 V or VDD; VINL or VINH

±1

µA max

Supply Current

IDD

All Digital Inputs VINL or VINH

All Digital Inputs 0 V or VDD

0.1

mA max

DC Supply Rejection

PSR

∆VDD = ±5%

0.002

%/% max

(

∆Gain/∆V

DD)

NOTES

1Measured using internal R

FB A and RFB B.

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

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