REV. A

PKD01

–13–

PEAK HOLD CAPACITOR RECOMMENDATIONS

and compensating capacitor. Stable operation requires a mini-

mum value of 1000 pF. Larger capacitors may be used to lower

droop rate errors, but acquisition time will increase.

mated with the following equation.

∆VmV

pC

CnF

mV

ZS

H

×

()

()

−

110

06

3

.

The peak hold capacitor should have very high insulation resis-

tance and low dielectric absorption. For temperatures below

85

°C, a polystyrene capacitor is recommended, while a Teflon

capacitor is recommended for high temperature environments.

CAPACITOR GUARDING AND GROUND LAYOUT

Ground planes are recommended to minimize ground path

resistance. Separate analog and digital grounds should be used.

The two ground systems are tied together only at the common

system ground. This avoids digital currents returning to the

system ground through the analog ground path.

PKD01

REPEAT ON

“COMPONENT SIDE”

OF PC BOARD IF POSSIBLE

BOTTOM VIEW

14

13

12

11

10

9

8

1

2

3

4

5

6

7

gain errors and maintain the PKD01’s inherently low droop rate,

guarding Pin 4 as shown in Figure 9 is recommended.

COMPARATOR

tors. It is possible to optimize noise immunity while interfacing

to all standard logic families—TTL, DTL, and CMOS. Figure

10 shows the comparator output with external level-setting

resistors. Table I gives typical R1 and R2 values for common

circuit conditions.

limited to:

CMP

PKD01

COMPARATOR

INPUT

INVERTING

COMPARATOR

INPUT

DIGITAL

GND

V–

R1 = R2

(

)

–1

R1

R2

Figure 10. Comparator Output with External Level-Setting

Resistors

Table I.

R1

R2

5

3.5

2.7 k

Ω 6.2 kΩ

5

5.0

2.7 k

Ω

15

3.5

4.7 k

Ω 1.5 kΩ

15

5.0

4.7 k

Ω 2.4 kΩ

15

7.5

7.5 k

Ω 7.5 kΩ

15

10.0

7.5 k

Ω 15 kΩ

PEAK DETECTOR LOGIC CONTROL (RST,

DET)

The transconductance amplifier outputs are controlled by the

digital logic signals RST and

DET. The PKD01 operational

thus providing high-speed switching and a predictable logic

threshold. The logic threshold voltage is 1.4 V when digital

ground is at zero volts.

the formula:

≈ 1.4 V + Digital Ground Potential.

For proper operation, digital ground must always be at least

3.5 V below the positive supply and 2.5 V above the negative

supply. The RST or

DET signal must always be at least 2.8 V

above the negative supply.

Operating the digital ground at other than zero volts does influence

to digital ground and will follow any changes in digital ground

potential:

≈ 0.2 V + Digital Ground Potential.

R

V

I

C

SINK

1

≈

R

V

V

C

OH

2

1

1

≈

−



















