A d v a nce d I n fo rm a t i o n

Eterna Datasheet

Linear Technology / Dust Networks

15

No

IPCS SPI /

FLASH

Programming

Type

I/O

Pull

Description

33

IPCS_MISO

2

O

-

SPI flash emulation (MISO) master in slave out port

GPIO6

I/O

-

General purpose digital I/O

35

IPCS_MOSI

1

I

-

SPI flash emulation (MOSI) master out slave in port

GPIO5

I/O

-

General purpose digital I/O

36

IPCS_SCK

1

I

-

SPI flash emulation (SCK) serial clock port

GPIO4

I/O

-

General purpose digital I/O

39

IPCS_SSn

1

I

-

SPI flash emulation slave select, active low

GPIO3

I/O

-

General purpose digital I/O

51

FLASH_P_ENn

I

UP

Flash program enable, active low

Note that this functionality is available only when RESETn is asserted

No

Special

Purpose Digital

Type

I/O

Pull

Description

27

SLEEPn

1*

I

-

Deep Sleep, active low

63

TIMEn

1*

I

-

Time capture request, active low

* Input signals that must be driven or pulled to a valid state to avoid leakage.

5.3

Power Supply

Eterna is powered from a single pin, VSUPPLY, and generates all required supplies internally. With two integrated DC/DC

converters and four voltage regulators, the sensitivity to noise on VSUPPLY is minimal. However, during typical operation

Eterna will vary its load on the power supply from the

μA range to 10’s of mA over a few μs. During such transients, the

power supply must meet the specifications for supply noise tolerance. Eterna is designed to operate with specific decoupling

capacitance on VCORE, VDDA, VOSC, VDDPA, and VPRIME, as well as the internal converter capacitors C1 through C4.

Failure to use correctly sized ceramic capacitors can result in supply instability and performance degradation.

5.3.1

Antenna

Eterna allows direct connection to a single-ended 50-Ohm antenna; an internal TX/RX switch simplifies external circuitry

requirements. Because both the transmit and the receive paths are single-ended, a balun (with its associated cost and

efficiency loss) are not required. Eterna provides options to set typical output power to 0 dBm or to +8 dBm using the on-chip

PA. For further details on radio transmit and receive, see section 2.4.

5.4

Analog

Eterna has four analog inputs. Its 10-bit ADC includes a 4-bit DAC for adjusting offset and a 3-bit VGA, as shown in Figure

13. The software application layer controls ADC operation and may be configured to automatically sample any combination

of the internal temperature sensor, or analog input signals.

Figure 13 Analog to Digital Chain

5.5

JTAG

Eterna includes an IEEE 1149.1-compliant JTAG port for boundary scan.