LTC1407A datasheet(11/20 Pages) LINER

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LTC2315-12

231512f

For more information www.linear.com/2315-12

applicaTions inForMaTion

threedifferenttimingschemes.DataisseriallyoutputMSB

first through LSB last, followed by trailing zeros if further

SCK falling edges are applied. Figure 5 illustrates that dur-

ing the case where SCK is held low during the acquisition

phase, only one leading zero is output. Figures 6 and 7

illustrate that for the SCK held high during acquisition or

continuous clocking mode two leading zeros are output.

Leading zeros allow the 12-bit data result to be framed

with both leading and trailing zeros for timing and data

verification. Since the rising edge of SCK will be coincident

with the falling edge of CS, delay t2 is the delay to the first

falling edge of SCK, which is simply 0.5 • tSCK. Delays t2

(CS falling edge to SCK leading edge) and t10 (14th falling

SCK edge to CS rising edge) must be observed for Figures

5, 6 and 7 and any timing implementation in order for the

conversion process and data readout to occur correctly.

The user can bring CS high after the 14th falling SCK edge

provided that timing delay t10 is observed. Prematurely

terminating the conversion by bringing CS high before

the 14th falling SCK edge plus delay t10 will cause a loss

of conversion data for that sample. The sample-and-hold

is placed in sample mode when CS is brought high. As

shown in Figure 6, a sample rate of 5Msps can be achieved

on the LTC2315-12 by using an 87.5MHz SCK data clock

and a minimum acquisition time of 40ns which results in

the minimum throughput time (tTHROUGHPUT) of 200ns.

Note that the maximum throughput of 5Msps can only be

achieved with the timing implementation of SCK held high

during acquisition as shown in Figure 6.

The LTC2315-12 also supports a continuous data clock

as shown in Figure 7. With a continuous data clock the

acquisition time period and conversion time period must

be designed as an exact integer number of data clock

periods. Because the minimum acquisition time is not an

exact multiple of the minimum SCK period, the maximum

sample rate for the continuous SCK timing is less than

5Msps. For example, a 4.86Msps throughput is achieved

usingexactly18dataclockperiodswiththemaximumdata

clock frequency of 87.5MHz. For this particular case, the

acquisition time period and conversion clock period are

designed as 4 data clock periods (TACQ = 45.7ns) and 14

data clock periods (TCONV = 160ns) respectively, yielding

a throughput time of 205.7ns.

The following table illustrates the maximum throughput

achievable for each of the three timing patterns. Note

that in order to achieve the maximum throughput rate of

5Msps, the timing pattern where SCK is held high during

the acquisition time must be used.

Table 1: Maximum Throughput vs Timing Pattern

TIMING PATTERN

MAXIMUM

THROUGHPUT

SCK high during TACQ

5Msps

SCK low during TACQ

4.86Msps

SCK continuous (tTHROUGHPUT = 18 periods)

4.86Msps

Serial Data Output (SDO)

The SDO output is always forced into the high impedance

state while CS is high. The falling edge of CS starts the

conversion and enables SDO. The A/D conversion result

is shifted out on the SDO pin as a serial data stream with

the MSB first. The data stream consists of either one

leading zero (SCK held low during acquisition, Fig. 5) or

two leading zeros (SCK held high during acquisition, Fig.

6) followed by 12 bits of conversion data. There is 1 cycle

of conversion latency. Subsequent falling SCK edges after

the LSB is output will output zeros on the SDO pin. The

SDO output returns to the high impedance state after the

16th falling edge of SCK.

The output swing on the SDO pin is controlled by the

OVDD pin voltage and supports a wide operating range

from 1.71V to 5.25V independent of the VDD pin voltage.

Power Considerations

The LTC2315-12 provides two sets of power supply pins:

the analog 5V power supply (VDD) and the digital input/

output interface power supply (OVDD). The flexible OVDD

supply allows the LTC2315-12 to communicate with any

digital logic operating between 1.8V and 5V, including

2.5V and 3.3V systems.

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