CA16 datasheet(23/30 Pages) AGERE

23 / 30 page

Agere Systems Inc.

Advance Data Sheet

CA16-Type 2.5 Gbits/s DWDM Transponder with

March 2001

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Timing Characteristics (continued)

PHERR/PHINIT

Case 1—PHERR and PHINIT are shorted on the

printed-circuit board:

PHINIT would go high whenever there is a potential tim-

ing mismatch between PCLK and PICLK. PHINIT would

remain high as long as the timing mismatch between

PCLK and PICLK. If PHINIT is high for more than two

byte clocks, the FIFO will be initialized. PHINIT will ini-

tialize the FIFO two-to-eight byte clocks after it is high

for at least two byte clocks, PHERR (and thus PHINIT)

goes active once the FIFI is initialized.

Case 2—PHERR signal is input to the customer logic

and the customer logic outputs a signal to PHINIT:

Another possible configuration is where the PHERR

signal is input into the customer logic and the customer

logic sends an output to the PHINIT input. However,

the customer logic must ensure that, upon detecting a

high on PHERR, the PHINIT signal remains high for

more than two byte clocks. If PHINIT is high for less

than two byte clocks, the FIFO is not guaranteed to be

initialized. Also, the customer logic must ensure that

PHINIT goes low after the FIFO is initialized (PHERR

goes low).

Figure 9. PHERR/PHINIT Timing

PHERR

PHINIT

PCLK

PICLK

INTERNAL

PCLK

MINIMUM PULSE

WIDTH REQUIRED

TO CENTER

THE FIFO

2 BYTE

CLOCKS

2—8 BYTE CLOCKS

CUSTOMER ASIC SENDS A

MINIMUM PULSE WIDTH OF

2 BYTE CLOCKS UPON DETECTING

A HIGH ON PHERR

FIFO IS INITIALIZED 2—8 BYTE CLOCKS

AFTER PHINIT IS HIGH FOR 2 BYTE CLOCKS

PHERR GOES HIGH ON

DETECTING A FIFO TIMING ERROR

1125(F)

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