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L7582 Datasheet(PDF) 13 Page - Agere Systems

Part # L7582
Description  Tip Ring Access Switch
PDF  16 Pages
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Manufacturer  AGERE [Agere Systems]
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L7582 Datasheet(HTML) 13 Page - Agere Systems

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Data Sheet
November 1999
Lucent Technologies Inc.
13
L7582 Tip Ring Access Switch
Application
12-2366.c (F)
Figure 7. Typical TRAS Application, Idle, or Talk State Shown
Table 13. Truth Table
1. If TSD = 5 V, the thermal shutdown mechanism is disabled. If TSD is floating, the thermal shutdown mechanism is active.
2. Forcing TSD to ground overrides the logic input pins and forces an all OFF state.
3. Idle/Talk state.
4. Power ringing state.
5. Test out or message waiting state.
6. All OFF state.
Input
Access
TSD
Tip
Break
Switch
Ring
Break
Switch
Ringing
Return
Switch
Ring
Switch
Tip
Access
Switch
Ring
Access
Switch
0 V
0 V
5 V/Float1
On
On
Off
Off
Off
Off3
5 V
0 V
5 V/Float1
Off
Off
On
On
Off
Off4
0 V
5 V
5 V/Float1
Off
Off
Off
Off
On
On5
5 V
5 V
5 V/Float1
Off
Off
Off
Off
Off
Off6
Don’t Care
Don’t Care
0 V2
Off
Off
Off
Off
Off
Off6
R2
TIP
TIP
RING
BATTERY
FEED
RING
GENERATOR
BATTERY
SW1 BREAK
SW5
LINE
TEST
ACCESS
SW3
RINGING
RETURN
SW2 BREAK
SW6
LINE
TEST
ACCESS
SW4
RINGING
ACCESS
R1
CROWBAR
PROTECTION
SCR
AND
TRIP
CKT
VBAT
REFERENCE
RING
A parallel in/parallel out data latch is integrated into the
L7582. Operation of the data latch is controlled by the
logic level input pin LATCH. The data input to the latch
is the INRING and INACCESS pins of the L7582, and the
output of the data latch is an internal node used for
state control.
When the LATCH control pin is at logic 0, the data latch
is transparent and data control signals flow directly
from INRING and INACCESS, through the data latch to
state control. Any changes in INRING and INACCESS will
be reflected in the state of the switches.
When the LATCH control pin is at logic 1, the data latch
is active—the L7582 will no longer react to changes at
the INRING and INACCESS control pins. The state of the
switches is now latched; that is, the state of the
switches will remain as they were when the LATCH
input transitioned from logic 0 to logic 1. The switches
will not respond to changes in INRING and INACCESS as
long as LATCH is held high.
Note that the TSD input is not tied to the data latch. TSD
is not affected by the LATCH input. TSD input will over-
ride state control via INRING, INACCESS, and LATCH.



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