T8207 datasheet(13/158 Pages) AGERE

13 / 158 page

Agere Systems Inc.

Advance Data Sheet

September 2001

ATM Interconnect

CelXpres T8207

Pin Description

This section defines the

CelXpres T8207 pins. All TTL compatible inputs or I/O are 5 V tolerant. No GTL+ inputs or

I/O are 5 V tolerant.

Table 1. UTOPIA Pins

Symbol

Ball

Reset

Value

Type

Name/Description

u_rxaddr[4:0]

R2, P3, R1, P2,

I/O

RX UTOPIA Address Lines. 10 mA drive, TTL compatible I/O,

5 V tolerant.

u_rxdata[7:0]

V2, U3, T4, V1,

U2, T3, U1, T2

—I

RX UTOPIA Data Lines. TTL compatible input, 5 V tolerant.

u_rxclk

I/O

RX UTOPIA Clock. 10 mA drive, TTL compatible I/O, 5 V tolerant.

u_rxsoc

—

RX UTOPIA Start of Cell (Active-High). TTL compatible input,

5 V tolerant.

u_rxclav[0]

I/O

RX UTOPIA PHY 0 Cell Available (Active-High). Main RX cell

available in single PHY mode. 10 mA drive, TTL compatible I/O, 5 V

tolerant. This pin has an internal 50 k

Ω pull-up resistor.

u_rxclav[3:1]

M3, M2, M1

—

RX UTOPIA Cell Available Lines (Active-High). TTL compatible

input, 5 V tolerant. These pins have an internal 50 k

Ω pull-up resis-

tor.

u_rxenb*[0]

I/O

RX UTOPIA PHY 0 Enable (Active-Low). Main RX enable in sin-

gle PHY mode. 10 mA drive, TTL compatible I/O, 5 V tolerant.

u_rxenb*[3:1]

N3, N2, N1

I/O

RX UTOPIA PHY Enable Lines (Active-Low). 10 mA drive, TTL

compatible I/O, 5 V tolerant.

u_rxprty

—

RX UTOPIA Odd Parity. TTL compatible input, 5 V tolerant. This

pin has an internal 50 k

Ω pull-up resistor.

u_txaddr[4:0]

P17, R19, R20,

P18, P19

I/O

TX UTOPIA Address Lines. 10 mA drive, TTL compatible I/O.

5 V tolerant.

u_txdata[7:0]

W20, V19, U19,

U18, T17, V20,

U20, T18

TX UTOPIA Data Lines. 10 mA drive, TTL compatible output.

u_txclk

R18

I/O

TX UTOPIA Clock. 10 mA drive, TTL compatible I/O, 5 V tolerant.

u_txsoc

T20

TX UTOPIA Start of Cell (Active-High). 10 mA drive, TTL compat-

ible output.

u_txclav[0]

M20

I/O

TX UTOPIA PHY 0 Cell Available (Active-High). Main TX cell

available in single PHY mode. 10 mA drive, TTL compatible I/O. 5 V

tolerant. This pin has an internal 50 k

Ω pull-up resistor.

u_txclav[3:1]

M17, M18, M19

—

TX UTOPIA Cell Available Lines (Active-High). TTL compatible

input, 5 V tolerant. These pins have an internal 50 k

Ω pull-up resis-

tor.

u_txenb*[0]

N20

I/O

TX UTOPIA PHY 0 Enable (Active-Low). Main TX enable in single

PHY mode. 10 mA drive, TTL compatible I/O, 5 V tolerant.

u_txenb*[3:1]

P20, N18, N19

TX UTOPIA Enable Lines (Active-Low). 10 mA drive, TTL com-

patible output.

u_txprty

T19

TX UTOPIA Odd Parity. 10 mA drive, TTL compatible output.

u_shr_o

V16

Shared UTOPIA Output. Used as grant if device is shared

UTOPIA master or as request if device is shared UTOPIA slave.

4 mA drive, TTL compatible output. This pin has an internal 50 k

Ω

pull-up resistor.

u_shr_i

W17

—

Shared UTOPIA Input. Used as request if device is shared

UTOPIA master or as grant if chip is shared UTOPIA slave. TTL

compatible input, 5 V tolerant. This pin has an internal 50 k

Ω pull-

up resistor.

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