T8302 datasheet(4/248 Pages) AGERE

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Table of Contents

Contents

Page

Agere Systems Inc.

T8302 Internet Protocol Telephone

Data Sheet

Advanced RISC Machine (ARM )

July 2001

1 Introduction ........................................................................................................................................................... 1

1.1 PT_ARM Features ........................................................................................................................................ 15

1.2 IPT_DSP Features .......................................................................................................................................16

2 Pinout Information ............................................................................................................................................... 17

2.1 272-Pin PBGA Pin Diagram ......................................................................................................................... 17

2.2 Pin List ..........................................................................................................................................................18

3 Overview ............................................................................................................................................................. 26

3.1 ARM 940T and AMBA Bridge ....................................................................................................................... 28

3.2 IPT_ARM Memory and I/O Map ................................................................................................................... 28

4 Reset/Clock Management ..................................................................................................................................29

4.1 Reset/Clock Management Controller Theory of Operation ........................................................................... 31

4.1.1 Reset Operation ..................................................................................................................................31

4.1.2 Operation of the Clock Switching Logic .............................................................................................. 32

4.1.2.1 PLL Operation ......................................................................................................................... 32

4.1.3 Latency ................................................................................................................................................ 33

4.1.4 Real-Time Clock (RTC) ....................................................................................................................... 33

4.2 Reset/Clock Management Registers ............................................................................................................ 35

4.2.1 Pause Register .................................................................................................................................... 35

4.2.2 Version ID Register ............................................................................................................................. 36

4.2.3 Clock Management Register ...............................................................................................................36

4.2.4 Clock Status Register .......................................................................................................................... 37

4.2.5 System Clock Source Encoding .......................................................................................................... 38

4.2.6 Clock Control Register ........................................................................................................................ 38

4.2.7 Soft Reset Register ............................................................................................................................. 38

4.2.8 PLL Control Register ...........................................................................................................................39

4.2.9 Reset Status (Control/Clear) Registers ............................................................................................... 40

4.2.10 Reset Peripheral Control (Read, Clear, Set) Registers ..................................................................... 40

4.2.11 RTC External Divider Register .......................................................................................................... 41

4.2.12 RTC Clock Prescale Registers .......................................................................................................... 42

4.2.13 RTC Control Register ........................................................................................................................ 43

4.2.14 RTC Seconds Alarm Register ........................................................................................................... 44

4.2.15 RTC Seconds Count Register ........................................................................................................... 44

4.2.16 RTC Divider Register ........................................................................................................................ 44

4.2.17 RTC Interrupt Status Register ........................................................................................................... 45

4.2.18 RTC Interrupt Enable Register .......................................................................................................... 45

4.3 Operation on Reset ...................................................................................................................................... 46

5 Programmable Interrupt Controller (PIC) ............................................................................................................ 47

5.1 Interrupt Controller Operation ....................................................................................................................... 47

5.1.1 Interrupt Registers ............................................................................................................................... 48

5.2 Programmable Interrupt Controller Registers ............................................................................................... 50

5.2.1 Interrupt Request Status Register IRSR ............................................................................................. 51

5.2.2 Interrupt Request Enable Registers IRER (Set, Clear) .......................................................................51

5.2.3 Interrupt Request Soft Register IRQSR .............................................................................................. 52

5.2.4 Interrupt Priority Control Registers IPCR[15:1] ................................................................................... 52

5.2.5 Interrupt In-Service Registers ISR (ISRI, ISRF) .................................................................................. 53

5.2.6 Interrupt Request Source Clear Register IRQESCR ........................................................................... 53

5.2.7 Interrupt Priority Enable Registers IPER (Set, Clear) .........................................................................54

5.2.8 External Interrupt Control Registers .................................................................................................... 55

6 Programmable Direct Memory Access (DMA) Controller ................................................................................... 56

6.1 DMA Operation ............................................................................................................................................. 56

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