ADAU1977WBCPZ-R7 datasheet(21/64 Pages) AD

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Data Sheet

ADAU1977

Rev. A | Page 21 of 64

ADC

The ADAU1977 contains four Δ-Σ ADC channels configured

as two stereo pairs with configurable differential/single-ended

inputs. The ADC can operate at a nominal sample rate of 32 kHz

up to 192 kHz. The ADCs include on-board digital antialiasing

filters with 79 dB stop-band attenuation and linear phase response.

Digital outputs are supplied through two serial data output pins

(one for each stereo pair) and a common frame clock (LRCLK)

and bit clock (BCLK). Alternatively, one of the TDM modes can

be used to support up to 16 channels on a single TDM data line.

With smaller amplitude input signals, a 10-bit programmable

digital gain compensation for an individual channel is provided

to scale up the output word to full scale. Care must be taken to

avoid overcompensation (large gain compensation), which leads

to clipping and THD degradation in the ADC.

The ADCs also have a dc-offset calibration algorithm to null

the systematic dc offset of the ADC. This feature is useful for dc

measurement applications.

ADC SUMMING MODES

The four ADCs can be grouped into either a single stereo ADC

or a single mono ADC to increase the signal-to-noise ratio (SNR)

for the application. Two options are available: one option for

summing two channels of the ADC and another option for

summing all four channels of the ADC. Summing is performed

in the digital block.

2-Channel Summing Mode

When the SUM_MODE Bits (Bits[7:6] of Register 0x0E) are

set to 01, the Channel 1 and Channel 2 ADC data are combined

and output from the SDATAOUT1 pin. Similarly, the Channel 3

and Channel 4 ADC data are combined and output from the

SDATAOUT2 pin. As a result, the SNR improves by 3 dB. For

this mode, both Channel 1 and Channel 2 must be connected to

the same input signal source. Similarly, Channel 3 and Channel 4

must be connected to the same input signal source.

4-Channel Summing Mode

When the SUM_MODE Bits (Bits[7:6] of Register 0x0E) are set

to 10, the Channel 1 through Channel 4 ADC data are combined

and output from the SDATAOUT1 pin. As a result, the SNR

improves by 6 dB. For this mode, all four channels must be

connected to the same input signal source.

DIAGNOSTICS

The diagnostics block monitors the input pins in real time and

reports a fault as an interrupt signal on the FAULT pin (Pin 8),

which triggers sending an interrupt request to an external

controller. The diagnostics status registers (Register 0x11 through

Refer to the register map table (Table 25) and the register details

tables (Table 42, Table 43, Table 44, and Table 45) for more infor-

mation about the diagnostics register content. The diagnostics

can be enabled or disabled for each channel using Bits[3:0] of

is enabled and the microphone is connected as recommended

in the appropriate application circuit (see Figure 21).

Diagnostics Reporting

The diagnostics status is reported individually for each channel

in Register 0x11 through Register 0x14. The faults listed in

Table 13 are reported on each input pin.

Table 13. Faults Reported

Fault

AINxP

AINxN

Short to Battery

Yes

Short to MICBIAS

Yes

Short to Ground

Yes

Short Between Positive and Negative Inputs

Yes

Open Input

Yes

Diagnostics Adjustments

Short Circuit to Battery Supply

When an input terminal is shorted to the battery, the voltage at

the terminal approaches the battery voltage. Any voltage higher

than the set threshold is reported as a fault. The threshold can

be set using the SHT_B_TRIP bits, Bits[1:0] of Register 0x17

(see Table 14).

Table 14. Setting the Short to Battery Threshold

SHT_B_TRIP

(Register 0x17, Bits[1:0])

Short to Battery Threshold

0.95 × VBAT

0.9 × VBAT

0.85 × VBAT

0.975 × VBAT

Short Circuit to MICBIAS

This feature is supported only on the AINxP terminal. When

an AINxP terminal is shorted to MICBIAS, the voltage at the

AINxP terminal approaches the MICBIAS voltage. Any voltage

higher than the set threshold is reported as a fault. The threshold

can be set using the SHT_M_TRIP bits, Bits[5:4] of Register 0x17

(see Table 15).

Table 15. Setting the Short to MICBIAS Threshold

SHT_M_TRIP

(Register 0x17, Bits[5:4])

Short to MICBIAS Threshold

0.95 × MICBIAS

0.9 × MICBIAS

0.85 × MICBIAS

0.975 × MICBIAS

Short Circuit to Ground

When an input terminal is shorted to ground, the terminal

voltage reaches close to 0 V. Any voltage lower than the set

threshold is reported as a fault. The threshold is referenced to

VREF and, therefore, scales with the voltage at the VREF pin.

ADAU1977WBCPZ-R7 Datasheet(PDF) 21 Page - Analog Devices

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