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ADV7610 Datasheet(PDF) 9 Page - Analog Devices

Part # ADV7610
Description  Low Power, 165 MHz HDMI Receiver
PDF  16 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV7610 Datasheet(HTML) 9 Page - Analog Devices

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Data Sheet
ADV7610
Rev. 0 | Page 9 of 16
Ball No.
Mnemonic
Type
Description
H1
P23
Digital video output
Video Pixel Output Port.
H2
P22
Digital video output
Video Pixel Output Port.
J1
P21
Digital video output
Video Pixel Output Port.
K1
P20
Digital video output
Video Pixel Output Port.
K2
P19
Digital video output
Video Pixel Output Port.
J2
P18
Digital video output
Video Pixel Output Port.
K3
P17
Digital video output
Video Pixel Output Port.
J3
P16
Digital video output
Video Pixel Output Port.
K4
LLC
Digital video output
Line Locked Output Clock for the Pixel Data the Range is 13.5 MHz to 162.5 MHz.
J4
P15
Digital video output
Video Pixel Output Port.
K5
P14
Digital video output
Video Pixel Output Port.
J5
P13
Digital video output
Video Pixel Output Port.
K6
P12
Digital video output
Video Pixel Output Port.
J6
P11
Digital video output
Video Pixel Output Port.
K7
P10
Digital video output
Video Pixel Output Port.
J7
P9
Digital video output
Video Pixel Output Port.
K8
P8
Digital video output
Video Pixel Output Port.
J8
P7
Digital video output
Video Pixel Output Port.
K9
P6
Digital video output
Video Pixel Output Port.
J9
P5
Digital video output
Video Pixel Output Port.
H10
P4
Digital video output
Video Pixel Output Port.
H9
P3
Digital video output
Video Pixel Output Port.
G10
P2
Digital video output
Video Pixel Output Port.
G9
P1
Digital video output
Video Pixel Output Port.
F10
P0
Digital video output
Video Pixel Output Port.
E10
DE
Miscellaneous digital
Data Enable. DE is a signal that indicates active pixel data.
F9
HS
Digital video output
Horizontal Synchronization Output Signal.
E9
VS/FIELD/ALSB
Digital input/output
Vertical Synchronization Output Signal.
Field Synchronization Output Signal in All Interlaced Video Modes.
VS or FIELD can be configured for this pin.
The ALSB allows selection of the I2C address.
D10, C10, D9, C9
I2S0 to I2S3
Miscellaneous digital
Audio Output Pins. These pins can be configured to output S/PDIF digital
audio (S/PDIF) or I2S.
A9
SCLK/INT2
Miscellaneous digital
A dual function pin that can be configured to output an audio serial clock or
an Interrupt 2 signal.
B9
LRCLK
Miscellaneous digital
Audio Left/Right Clock.
A8
MCLK/INT2
Miscellaneous digital
A dual function pin that can be configured to output an audio master clock or
an Interrupt 2 signal.
B8
SCL
Miscellaneous digital
I2C Port Serial Clock Input. SCL is the clock line for the control port.
B7
SDA
Miscellaneous digital
I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
A7
INT1
Miscellaneous digital
Interrupt 1. This pin can be active low or active high. When status bits change, this
pin is triggered. The events that trigger an interrupt are under user configuration.
B6
RESET
Miscellaneous digital
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is
required to reset the ADV7610 circuitry.
A6
XTALP
Miscellaneous analog
Input Pin for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock
Oscillator Source to Clock the ADV7610.
A5
XTALN
Miscellaneous analog
Crystal Input. Input pin for 28.63636 MHz crystal.
B4
CEC
Digital input/output
Consumer Electronic Control Channel.
B5
CS
Miscellaneous digital
Chip Select (Bar). Pulling this line high causes the I2C state machine to ignore
the I2C transmission.
A3
DDCA_SCL
HDMI input
HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
B3
DDCA_SDA
HDMI input
HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant.
A2
RXA_5V
HDMI input
5 V Detect Pin for Port A in the HDMI Interface.



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