MPC2002

•MPC2003

8

MOTOROLA FAST SRAM

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . . . .

Input Pulse Levels

0 to 3.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time

3 ns

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level

1.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load

See Figure 1A Unless Otherwise Noted

. . . . . . . . . . . .

MPC2002SG66/

MPC2003SG66

MPC2002SG60/

MPC2003SG60

MPC2002SG50/

MPC2003SG50

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Cycle Time

tKHKH

15

—

16.6

—

20

—

ns

Clock Access Time

tKHQV

—

9

—

11

—

14

ns

4

Output Enable to Output Valid

tGLQV

—

5

—

5

—

6

ns

Clock High to Output Active

tKHQX1

6

—

6

—

6

—

ns

Clock High to Output Change

tKHQX2

3

—

3

—

3

—

ns

Output Enable to Output

Active

tGLQX

0

—

0

—

0

—

ns

Output Disable to Q High–Z

tGHQZ

2

6

2

6

2

6

ns

5

Clock High to Q High–Z

tKHQZ

—

6

—

6

—

6

ns

5

Clock High Pulse Width

tKHKL

5

—

5

—

6

—

ns

Clock Low Pulse Width

tKLKH

5

—

5

—

6

—

ns

Setup Times:

Address

Address Status

Data In

Write

Address Advance

Chip Select

tAVKH

tTSVKH

tDVKH

tWVKH

tBAVKH

tEVKH

2.5

—

2.5

—

2.5

—

ns

6

Hold Times:

Address

Address Status

Data In

Write

Address Advance

Chip Select

tKHAX

tKHTSX

tKHDX

tKHWX

tKHBAX

tKHEX

0.5

—

0.5

—

0.5

—

ns

6

NOTES:

1. A read cycle is defined by UW and LW high or TSP low for the setup and hold times. A write cycle is defined by LW or UW low and TSP high

for the setup and hold times.

2. All read and write cycle timings are referenced from K or G.

3. G is a don’t care when UW or LW is sampled low.

4. Maximum access times are guaranteed for all possible PowerPC 60x external bus cycles.

5. Transition is measured

± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any

given voltage and temperature, tKHQZ max is less than tKHQX1 min for a given device and from device to device.

6. This is a synchronous device. All addresses must meet the specified setup and hold times for

ALL rising edges of clock (K) whenever TSP

or TSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for

ALL rising edges of

K when the chip is selected.Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain enabled.

AC TEST LOADS

Figure 1A

Figure 1B

5 pF

+ 5 V

OUTPUT

480

Ω

255

Ω

OUTPUT

Z0 = 50 Ω

RL = 50 Ω

VL = 1.5 V