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MPC2004 Datasheet(PDF) 5 Page - Motorola, Inc

Part # MPC2004
Description  256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms
PDF  6 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MPC2004 Datasheet(HTML) 5 Page - Motorola, Inc

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MPC2004
•MPC2005
6–5
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
68, 69, 70, 71, 73, 74, 75,
76, 78, 79, 80, 82, 83, 84,
85, 159, 160, 161, 162,
164, 165, 166, 167, 169,
170, 171, 173, 174, 175
A0 – A28
Input
Address Inputs – (MSB:0, LSB:28)
62, 63
ADDR0A,
ADDR0B
Input
Least significant address bit when asynchronous SRAMs are used.
153, 154
ADDR1A,
ADDR1B
Input
Next to least significant address bit when asynchronous SRAMs are used.
30, 56, 117, 146, 148
CLK0 – CLK4
Input
Clock Inputs – CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for SRAMs.
For 1MB use all the clocks. For 512KB or less us CLK0–CLK2 only.
4, 5, 6, 7, 10, 11, 12, 14,
16, 17, 19, 20, 22, 24, 25,
26, 27, 95, 96, 97, 98, 101,
102, 103, 105, 107, 108,
110, 111, 113, 115, 119
DH0 – DH31
I/O
High Data Bus – (MSB:0, LSB:31)
32, 33, 34, 37, 38, 39, 40,
43, 44, 45, 47, 49, 50, 52,
53, 54, 121, 122, 124, 125,
126, 129, 130, 131, 133,
135, 136, 138, 139, 141,
143, 144
DL0 – DL31
I/O
Low Data Bus – (MSB:0, LSB:31)
9, 15, 21, 28, 35, 42, 48, 58
DP0 – DP7
I/O
Data Parity Bus – (MSB:0, LSB:7)
3, 94
PD2, PD3
Output
Presence detect bits 2 and 3.
2
PD0/IDSCLK
Input
Presence detect bit 0/EEPROM serial clock.
93
PD1/IDSDATA
I/O
Presence detect bit 1/EEPROM serial data.
64, 65
SRAMADS0,
SRAMADS1
Input
SRAM Address Strobe – For 512KB or less us SRAM ADS0 only.
151
SRAM ALE
Input
SRAM Address Latch Enable – Use for asynchronous SRAM only.
155, 156
SRAMCNTEN0,
SRAMCNTEN1
Input
SRAM Count Enables – For 512KB or less use SRAM CNT EN0 only.
59, 60
SRAMOE0,
SRAMOE1
Input
SRAM Output Enables – For 512KB or less use SRAM OE0 only.
100, 106, 112, 120, 128,
134, 140, 150
SRAMWE0 –
SRAMWE7
Input
SRAM Write Enables – (MSB:0, LSB:7)
87
TAGCLR
Input
Tag RAM clear.
88
TAG MATCH
Output
Tag RAM match indication.
178
TAG VALID
Input
Tag RAM valid bit.
179
TAGWE
Input
Tag RAM write enable.
89
TAGOE
Input
Tag RAM output enable.
90
DIRTYIN
Input
Dirty input bit.
181
DIRTYOUT
Output
Dirty output bit.
180
STANDBY
Input
Standby pin. Reduces standby power consumption.
176
RESERVED
Reserved pin.
8, 23, 51, 61, 77, 99, 114,
142, 152, 168
VCC3
Input
+ 3.3 V power supply.



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