MPC9140

MOTOROLA

TIMING SOLUTIONS

BR1333 — REV 5

2

Figure 2. Block Diagram

SDRAM0

SDRAM1

SDRAM2

SDRAM3

SDRAM4:13

SDRAM14

SDRAM15

SDRAM16

SDRAM17

CONFIG

REGISTERS

I2C

INTERFACE

SDATA

SCLOCK

OE

18

10

10

10

BUF_IN

Table 1. Pin Descriptions

Pin Name

I/O

Function

BUF_IN

I

3.3V CMOS clock input

SDRAM0:17

O

3.3V CMOS SDRAM clock outputs

SDATA

I/O

Serial data for configuration control

SCLK

I

Serial clock input for configuration control. The state of the SDATA input is clocked into the device on

the rising edge of this clock

OE

I

A Low forces all outputs into High–Z state

VDD

–

3.3V power supply connection

VSS

–

Ground connection which should be connected directly to the ground plane