MPC952

MOTOROLA

ECLinPS and ECLinPS Lite

DL140 — Rev 3

4

AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

tr, tf

Output Rise/Fall Time (Note 4.)

0.10

1.0

ns

0.8 to 2.0V

tpw

Output Pulse Width (Note 4.)

tCYCLE/2

–750

tCYCLE/2

±500

tCYCLE/2

+750

ps

tos

Output-to-Output Skew

Excluding Qa0

(Note 4.)

All Outputs

All Outputs

350

450

550

ps

Same Frequencies

Same Frequencies

Different Frequencies

fVCO

PLL VCO Lock Range

Feedback = VCO/4

Feedback = VCO/6

Feedback = VCO/8

Feedback = VCO/12

200

200

200

200

480

480

480

480

MHz

VCO_Sel = 0

VCO_Sel = 0

VCO_Sel = 1

VCO_Sel = 1

fmax

Maximum Output Frequency

Qc,Qb (

÷2)

Qa,Qb,Qc (

÷4)

Qa (

÷6)

180

120

80

MHz

(Note 4.)

tpd

REFCLK to FBIN Delay

–200

0

200

ps

Notes 4., 5.

tPLZ, tPHZ

Output Disable Time

2

8

ns

50

Ω to VCC/2

tPZL, tPLH

Output Enable Time

2

10

ns

50

Ω to VCC/2

tjitter

Cycle–to–Cycle Jitter (Peak–to–Peak)

±100

ps

tlock

Maximum PLL Lock Time

10

ms

4. 50

Ω to VCC/2.

5. tpd is specified for 50MHz input ref, the window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods.

The tpd does not include jitter.

APPLICATIONS INFORMATION

Driving Transmission Lines

The MPC952 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 10

Ω the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to application note AN1091 in the

Timing Solutions brochure (BR1333/D).

Figure 3. Single versus Dual Transmission Lines

7

Ω

IN

MPC952

OUTPUT

BUFFER

RS = 43Ω

ZO = 50Ω

OutA

7

Ω

IN

MPC952

OUTPUT

BUFFER

RS = 43Ω

ZO = 50Ω

OutB0

RS = 43Ω

ZO = 50Ω

OutB1

In most high performance clock networks point–to–point

distribution of signals is the method of choice. In a

point–to–point scheme either series terminated or parallel

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

50

Ω resistance to VCC/2. This technique draws a fairly high

level of DC current and thus only a single terminated line can

be driven by each output of the MPC952 clock driver. For the

series terminated case however there is no DC current draw,

thus the outputs can drive multiple series terminated lines.

Figure 3 illustrates an output driving a single series

terminated line vs two series terminated lines in parallel.

When taken to its extreme the fanout of the MPC952 clock

driver is effectively doubled due to its capability to drive

multiple lines.

The waveform plots of Figure 4 show the simulation

results of an output driving a single line vs two lines. In both

cases the drive capability of the MPC952 output buffers is

more than sufficient to drive 50

Ω transmission lines on the

incident edge. Note from the delay measurements in the

simulations a delta of only 43ps exists between the two

differently loaded outputs. This suggests that the dual line

driving need not be used exclusively to maintain the tight

output–to–output skew of the MPC952. The output waveform

in Figure 4 shows a step in the waveform, this step is caused

by the impedance mismatch seen looking into the driver. The

parallel combination of the 43

Ω series resistor plus the output

impedance does not match the parallel combination of the

line impedances. The voltage wave launched down the two

lines will equal: