MPC970

TIMING SOLUTIONS

BR1333 — Rev 6

7

MOTOROLA

DETAILED PIN DESCRIPTIONS

The following gives a brief description of the functionality

of the MPC970 I/O. Unless explicitly stated all inputs are

LVCMOS/LVTTL compatible with internal pull up resistors. All

outputs are LVCMOS level outputs which are capable of

driving two series terminated 50

Ω transmission lines on the

incident edge.

xtal1, xtal2

For the MPC970 the xtal1 and xtal2 pins represent the

external crystal connections to the internal oscillator. The

crystal oscillator is completely self contained, there are no

external components required. The oscillator is specified to

function for crystals of up to 50MHz. Exact crystal

specifications are outlined in the applications section.

VCO_Sel

The VCO_Sel pin allows the user to further divide the

internal VCO frequency for the generation of lower

frequencies at the outputs. The VCO_Sel pin should be used

to set the VCO into its most optimum range. Refer to the

applications section for more details on the VCO frequency

range. A logic ‘1’ on the VCO_Sel pin will bypass the internal

÷2.

TClk

The TClk input serves a dual purpose; it can be used as

either a reference clock input for the PLL from an external

frequency source or it can be used as a board level test clock

in the PLL bypass mode.

PLL_En

The PLL_En pin allows the TClk input to be routed around

the PLL for system test and debug. When pulled low the

MPC970 will be placed in the test mode. Note that the TClk

input will be routed through the divider chain. For instance in

the PowerPC 601 microprocessor clock generation mode the

TClk input will toggle twice for each toggle on the 2x_PCLK

output. Depending on the states of the frequency divider

select pins this ratio may be higher.

Frz_Data

Frz_Data is the serial data input for the output freeze

function of the device. Refer to the applications section for

more information on the freeze functionality.

Frz_Clk

Frz_Clk is the serial freeze logic clock input. Refer to the

applications section for more information on the freeze

functionality.

Frz_Strobe

The Frz_Strobe input is used to freeze or unfreeze all of

the outputs simultaneously. Refer to the applications section

for more information on the freeze functionality.

Com_Frz

The Com_Frz input allows the user to enable/disable all of

the outputs with the control of a single pin. The action will

take place upon a high to low transition of the Frz_Strobe

input.

BClk_Div0:1

The BClk_Div inputs are used to program the VCO divide

ratio for the BCLK outputs. These inputs also set the divide

ratio of the BCLKEN output to be equal in frequency to the

BCLK outputs when the device is in the MPC601_Clks mode.

The BClk_Div inputs set the frequency as follows:

BClk_Div1

BClk_Div0

BCLK Frequency

0

0

1

1

0

1

0

1

PCLKEN

PCLKEN/2

PCLKEN/3

PCLKEN/4

In most applications these inputs will be strapped to the

appropriate power rails.

PCI_Div0:1

The PCI_Div inputs set the division ratio for the

PCI_CLKs. The PCI_CLKs are set relative to the BCLK or the

PCLKEN output such that you can upgrade the processor

bus and maintain the PCI bus frequency in the currently

defined

≤ 33MHz range. The PCI_Div inputs set the

PCI_CLKs as follows:

PCI_Div1

PCI_Div0

PCI_CLK Frequency

0

0

1

1

0

1

0

1

BCLK

BCLK/2

BCLK/3

PCLKEN

In a typical application these inputs will be strapped to the

appropriate power rail.

MPC601_Clks

The MPC601_Clks input will configure the outputs to drive

the PowerPC 601 microprocessor when pulled HIGH or left

open. When pulled LOW it will configure the 2xPCLK,

PCLKEN and BCLKEN all into a VCO/4 mode. In this mode

the MPC970 will have three more outputs available to drive

clock loads on the processor bus for PowerPC 603,

PowerPC 604 or Pentium microprocessor based systems.

Ext_FB

The Ext_FB pin is an input to the phase detector of the PLL

which is tied to an external feedback output. Typically this

feedback will be one of the lowest frequency outputs of the

MPC970.

IntFB_Sel

The IntFB_Sel input selects whether the internal feedback

signal or an external feedback signal is routed to the phase

detector of the PLL. The default mode, pulled HIGH via the

internal pull up resistor, is to select the internal feedback.