MPC992

MOTOROLA

TIMING SOLUTIONS

BR1333 — REV 5

6

capacitors to the buried power planes. Fat interconnect and

large vias will help to minimize layout induced inductance and

thus maximize the series resonant point of the bypass

capacitors.

No active signal lines should pass below the crystal

interface to the MPC992. The oscillator is a series resonant

circuit and the voltage amplitude across the crystal is

relatively small. It is imperative that no actively switching

signals cross under the crystal as crosstalk energy coupled

to these lines could significantly impact the jitter of the device.

Special attention should be paid to the layout of the crystal to

ensure a stable, jitter free interface between the crystal and

the on–board oscillator. In addition, the crystal interface

circuitry will be adversely affected by activity on the

PECL_CLK inputs. Therefore, it is recommended that the

PECL input signals be static when the crystal oscillator

circuitry is being used.

Although the MPC992 has several design features to

minimize the susceptibility to power supply noise (isolated

power and grounds and fully differential PLL) there still may

be applications in which overall performance is being

degraded due to system power supply noise. The power

supply filter and bypass schemes discussed in this section

should be adequate to eliminate power supply noise related

problems in most designs.