DA82562EM datasheet(21/40 Pages) INTEL

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Networking Silicon — 82562ET

Datasheet

5.0

Platform LAN Connect Registers

The following subsections describe PHY registers that are accessible through the LAN Connect

management frame protocol.

Acronyms mentioned in the registers are defined as follows:

SC:

Self cleared.

RO:

Read only.

RW:

Read/Write.

EEPROM setting affects content.

LL:

Latch low.

LH:

Latch high.

5.1

Medium Dependent Interface Registers 0 through 7

5.1.1

Bit(s)

Name

Description

Default

R/W

Reset

This bit sets the status and control register of the PHY to

their default states and is self-clearing. The PHY returns

a value of one until the reset process has completed and

accepts a read or write transaction.

0 = Normal operation

1 = PHY Reset

0RW

Loopback

This bit enables loopback of transmit data nibbles to the

receive data path. The PHY receive circuitry is isolated

from the network.

Note that this may cause the descrambler to lose

synchronization and produce 560 nanoseconds of “dead

time.”

Note also that the loopback configuration bit takes priority

over the Loopback MDI bit.

0 = Loopback disabled (normal operation)

1 = 1 = Loopback enabled

0RW

Speed Selection

This bit is valid on read and controls speed when Auto-

Negotiation is disabled.

0 = 10 Mbps

1 = 100 Mbps

1RW

Auto-Negotiation

Enable

This bit enables Auto-Negotiation. Bits 13 and 8, Speed

Selection and Duplex Mode, respectively, are ignored

when Auto-Negotiation is enabled.

0 = Auto-Negotiation disabled

1 = Auto-Negotiation enabled

1RW

Reduced Power

Down

This bit sets the PHY into a low power mode.

0 = Power down disabled (normal operation)

1 = Power down enabled

0RW

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