Since R

, quiescent current, and switching

losses all vary with input voltage, the total losses

should be investigated over the complete input

voltage range. The maximum power dissipation

d e p e n d s o n t h e t h e r m a l r e si st a n c e o f I C

package, PCB layout, the rate of surrounding

airflow and temperature difference between

junction and ambient. The maximum power

dissipation can be calculated by the following

formula:

Where TJ(ma x) is the m aximu m allo wable

junction temperature 125°C.T

is the ambient

tempera ture and

is the thermal resistance

from the junction to the ambient. Based on the

standard JEDEC for a two layers thermal test

board, the thermal resistance

of WDFN3X3 is

60°C/W. The maximum power dissipation at T =

25°C can be calculated by following formula:

P =(125°C-25°C)/60°C/W=1.67W

The internal reference is 0.6V (Typical). The

output voltage is calculated as below:

The output voltage is given by Table 1.

Resistor selection for output voltage

setting

When load current decreases, the peak swi tch

current in Power-PMOS will be lower than skip

current threshold and the device will enter into

Pulse Skipping Mode.

In this mode, the device has two states, working

state and idle state. First, the device enters into

w o r k in g s t a t e c o n t ro ll e d b y in t e r n a l e r ro r

amplifier.When the feedback voltage gets higher

than internal reference voltage, the device will

enter into low I

idle state with most of internal

blocks disabled. The output voltage will be

reduced by loading or leakage current. When the

feedback voltage gets lower than the internal

reference voltage, the convertor will start a

working state again.

As the input voltage approaches the output

voltage, the converter turns the P-chan nel

transistor continuously on. In this mode the

output voltage is equal to the input voltage minus

th e vo lt a g e d ro p a c ro s s t h e P - c h a n n e l

transistor:

V

= V –I

(R

+ R )

where R

= P-channel switch ON resistance,

I

= O u t p u t c u rr e n t , R

= I n d u c t o r D C

resistance.

The reference and the circuit remain reset un til

the VIN crosses its UVLO threshold.

The PAM2319 has an internal soft-start circuit

that limits the in-rush current during start-up.

This prevents possible voltage drops of the input

volt ag e an d elim ina t es t he o ut p ut volt a ge

overshoot.

When the die temperature exceeds 150°C, a

reset occurs and the reset remains until the

temperature decrease to 120°C, at which time

the circuit can be restarted.

DS(ON)

A

JA

JA

A

D

Q

OUT

IN

LOAD

dson

L

dson

L O A D

L

θ

θ

Setting the Output Voltage

Table 1:

Pulse Skipping Mode (PSM) Description

100% Duty Cycle Operation

UVLO and Soft-Start

Thermal Shutdown













O

R1

V =0.6×1+

R2

Vo

R1

R2

1.2V

150k

150k

1.5V

150k

100k

1.8V

300k

150k

2.5V

380k

120k

3.3V

680k

150k

J(MAX)

A

D

JA

T

-T

P =

θ

10

,

Power Analog Microelectronics Inc

www.poweranalog.com

PAM2319

Dual High-Efficiency PWM Step-Down DC-DC Coverter

12/2011 Rev1.1