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INTEDG Datasheet(PDF) 223 Page - Microchip Technology |
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INTEDG Datasheet(HTML) 223 Page - Microchip Technology |
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223 / 478 page  2010-2012 Microchip Technology Inc. DS41414D-page 223 PIC16(L)F1946/47 23.3.7 OPERATION IN SLEEP MODE In Sleep mode, the TMRx register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMRx will continue from its previous state. 23.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 5.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details. 23.3.9 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 23.3.10 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a reset, see Section 12.1 “Alternate Pin Function” for more information. TABLE 23-8: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 238 CCPTMRS0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 239 CCPTMRS1 — — — — — — C5TSEL<1:0> 239 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 93 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE C3IE CCP2IE 94 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 95 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 97 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF C3IF CCP2IF 98 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 99 PR2 Timer2 Period Register 211* PR4 Timer4Period Register 211* PR6 Timer6 Period Register 211* T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<:0>1 213 T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<:0>1 213 T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<:0>1 213 TMR2 Timer2 Module Register 211* TMR4 Timer4 Module Register 211* TMR6 Timer6 Module Register 211* TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 131 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 134 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 137 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 140 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 143 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. Note 1: Applies to ECCP modules only. * Page provides register information. |
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