MCP47DA1 datasheet(49/76 Pages) MICROCHIP

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 2012-2013 Microchip Technology Inc.

DS25118D-page 49

MCP47DA1

7.4

Output Errors

The output error is caused by two factors. These are:

• Characteristics of the Resistor Network

• Characteristics of the Output Buffer

Figure 7-5 shows the components of the error on the

output voltage. The first part of the error is from the

resistor ladder and the RFS and RZS resistances. The

second part is due to the output buffer’s input offset

characteristics.

The RFS and RZS resistances effect the voltage

between VZS and VFS. The larger that RFS + RZS is, the

smaller that the step voltage (VS) will be (from the

theoretical step voltage). The increase in the RFS and

RZS resistances also effects the Full-Scale Error (FSE),

Zero-Scale Error (ZSE), and gain error.

Table 7-4 compares theoretical resistor network volt-

ages for full scale and zero scale, where RFS = RZS =

, to an example where RFS and RZS and non-zero.

The voltage calculations show cases of VREF = 5.0V

and VREF = 1.5V. Figure 2-89 shows RVREF, RFS, and

RZS resistances VDD.

So, as the voltage reference (VREF) decreases, the

Step voltages (VS) decrease. At a low VREF voltage, the

step voltage approaches the magnitude of the output

buffer’s input offset voltage (design target of ± 4.5 mV).

So, for low VREF voltages, the output buffer errors have

greater influence on the VOUT voltage.

TABLE 7-4:

CALCULATION COMPARISON

FIGURE 7-5:

Output Voltage (VOUT) Error.

Example Theoretical

Delta

RVREF

30,180



—

RFS

100



100



RZS



R1 + 64*RS +

30,000



30,180



- 180



R1, RAB, R2

10,000



10,060



- 60



VREF

5.00 V

—

VFS

3.3267 V

3.3333 V

- 6.6 mV

VZS

1.6700 V

1.6667 V

+ 3.3 mV

25.88 mV

26.04 mV

- 0.16 mV

VREF

1.5V

—

VFS

0.9980 V

1.0000 V

- 2.0 mV

VZS

0.5010 V

0.5000 V

+ 1.0 mV

7.766 mV

7.813 mV

-0.047mV

Note 1: RVREF = R1 + RAB + R2 ,

RAB = RFS + 64*RS + RZS.

VS = (VFS - VZS) / 64

VREF

VSS

( RFS  0 )

( RZS  0 )

Theoretical VFS ( (2/3) * VREF )

Theoretical VZS ( (1/3) * VREF )

VFS-RL

VZS-RL

Variations due to Output Buffer’s

Input Offset voltage

(Due to RFS  0)

VOUT(FS)

VOUT(ZS)

(Due to RZS  0)

Step Voltage (VS) =

* VREF

(VFS - VZS)

VS = VREF / 192

VREF

26.0mV 14.1mV

9.4mV

7.8mV 5.2mV

5.0V

2.7V

1.8V

1.5V

1.0V

when RFS = RZS = 0 .

When:

RFS = RZS = 0 .

VFS-RL should be less than VDD - 1.0V

(due to buffer input not being rail-to-rail, not

meeting this requirement would only effect

VOUT linearity at upper codes)

and Buffer ‘s Impedance/Load.

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