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PIC16F87 Datasheet(PDF) 217 Page - Microchip Technology |
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PIC16F87 Datasheet(HTML) 217 Page - Microchip Technology |
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217 / 230 page  2002-2013 Microchip Technology Inc. DS30487D-page 217 PIC16F87/88 INDEX A A/D Acquisition Requirements ........................................ 119 ADIF Bit .................................................................... 118 Analog-to-Digital Converter ...................................... 115 Associated Registers ............................................... 122 Calculating Acquisition Time .................................... 119 Configuring Analog Port Pins ................................... 121 Configuring the Interrupt .......................................... 118 Configuring the Module ............................................ 118 Conversion Clock ..................................................... 120 Conversions ............................................................. 121 Converter Characteristics ........................................ 190 Delays ...................................................................... 119 Effects of a Reset ..................................................... 122 GO/DONE Bit ........................................................... 118 Internal Sampling Switch (Rss) Impedance ............. 119 Operation During Sleep ........................................... 122 Operation in Power-Managed Modes ...................... 120 Result Registers ....................................................... 121 Source Impedance ................................................... 119 Time Delays ............................................................. 119 Using the CCP Trigger ............................................. 122 Absolute Maximum Ratings ............................................. 163 ACK .................................................................................... 95 ADCON0 Register ...................................................... 16, 115 ADCON1 Register ...................................................... 17, 115 Addressable Universal Synchronous Asynchronous Receiver Transmitter. See AUSART ADRESH Register ...................................................... 16, 115 ADRESH, ADRESL Register Pair .................................... 118 ADRESL Register ...................................................... 17, 115 ANSEL Register ............................................. 17, 54, 60, 115 Application Notes AN556 (Implementing a Table Read) ........................ 27 AN578 (Use of the SSP Module in the I2C Multi-Master Environment) ..................................................... 89 AN607 (Power-up Trouble Shooting) ....................... 135 Assembler MPASM Assembler .................................................. 160 Asynchronous Reception Associated Registers ....................................... 107, 109 Asynchronous Transmission Associated Registers ............................................... 105 AUSART ............................................................................ 99 Address Detect Enable (ADDEN Bit) ....................... 100 Asynchronous Mode ................................................ 104 Asynchronous Receive (9-bit Mode) ........................ 108 Asynchronous Receive with Address Detect. See Asyn- chronous Receive (9-Bit Mode). Asynchronous Receiver ........................................... 106 Asynchronous Reception ......................................... 107 Asynchronous Transmitter ....................................... 104 Baud Rate Generator (BRG) ................................... 101 Baud Rate Formula ......................................... 101 Baud Rates, Asynchronous Mode (BRGH = 0) 102 Baud Rates, Asynchronous Mode (BRGH = 1) 102 High Baud Rate Select (BRGH Bit) ................... 99 INTRC Baud Rates, Asynchronous Mode (BRGH = 0) ............................................................. 103 INTRC Baud Rates, Asynchronous Mode (BRGH = 1) ............................................................. 103 INTRC Operation ............................................. 101 Low-Power Mode Operation ............................ 101 Sampling ......................................................... 101 Clock Source Select (CSRC Bit) ............................... 99 Continuous Receive Enable (CREN Bit) ................. 100 Framing Error (FERR Bit) ........................................ 100 Mode Select (SYNC Bit) ............................................ 99 Receive Data, 9th bit (RX9D Bit) ............................. 100 Receive Enable, 9-bit (RX9 Bit) ............................... 100 Serial Port Enable (SPEN Bit) ........................... 99, 100 Single Receive Enable (SREN Bit) .......................... 100 Synchronous Master Mode ...................................... 110 Synchronous Master Reception .............................. 112 Synchronous Master Transmission ......................... 110 Synchronous Slave Mode ........................................ 113 Synchronous Slave Reception ................................ 114 Synchronous Slave Transmit ................................... 113 Transmit Data, 9th Bit (TX9D) ................................... 99 Transmit Enable (TXEN Bit) ...................................... 99 Transmit Enable, Nine-bit (TX9 Bit) ........................... 99 Transmit Shift Register Status (TRMT Bit) ................ 99 B Baud Rate Generator Associated Registers ............................................... 101 BF Bit ................................................................................. 95 Block Diagrams A/D ........................................................................... 118 Analog Input Model .......................................... 119, 127 AUSART Receive ............................................ 106, 108 AUSART Transmit ................................................... 104 Capture Mode Operation ........................................... 84 Comparator I/O Operating Modes ........................... 124 Comparator Output .................................................. 126 Comparator Voltage Reference ............................... 130 Compare Mode Operation ......................................... 85 Fail-Safe Clock Monitor ........................................... 146 In-Circuit Serial Programming Connections ............ 149 Interrupt Logic .......................................................... 141 On-Chip Reset Circuit .............................................. 134 PIC16F87 .................................................................... 8 PIC16F88 .................................................................... 9 RA0/AN0:RA1/AN1 Pins ............................................ 54 RA2/AN2/CVref/Vref- Pin .......................................... 55 RA3/AN3/Vref+/C1OUT Pin ....................................... 55 RA4/AN4/T0CKI/C2OUT Pin ..................................... 56 RA5/MCLR/Vpp Pin ................................................... 56 RA6/OSC2/CLKO Pin ................................................ 57 RA7/OSC1/CLKI Pin .................................................. 58 RB0/INT/CCP1 Pin .................................................... 61 RB1/SDI/SDA Pin ...................................................... 62 RB2/SDO/RX/DT Pin ................................................. 63 RB3/PGM/CCP1 Pin .................................................. 64 RB4/SCK/SCL Pin ..................................................... 65 |
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