Data Sheet

AD9888

Rev. C | Page 21 of 36

2-WIRE SERIAL REGISTER MAP

The AD9888 is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to

write and read the control registers through the two-line serial interface port.

Table 8. Control Register Map

Hex

Address

Read and

Write, or

Read Only

Bits

Default

Value

Register Name

Function

0x00

RO

[7:0]

Chip revision

An 8-bit register that represents the silicon revision level.

0x01

R/W

[7:0]

01101001

PLL divider MSB

MSBs (Bits[11:4]) of the PLL divider word. Larger values mean the PLL

operates at a faster rate. This register should be loaded first whenever a

change is needed to allow the PLL more time to lock.1

0x02

R/W

[7:4]

1101****

PLL divider LSB

LSBs of the PLL divider word.1

0x03

R/W

[7:3]

01******

VCO range

select/charge

pump current

Bits[7:6]—VCO range. Selects VCO frequency range. See the Clock

Generation section.

**001***

Bits[5:3]—charge pump current. Varies the current that drives the low-

pass filter. See the Clock Generation section.

0x04

R/W

[7:3]

10000***

Clock Phase

adjust

ADC Clock phase adjustment. Larger values mean more delay.

(1 LSB = t/32)

0x05

R/W

[7:0]

00001000

Clamp

placement

Places the CLAMP signal an integer number of clock periods after the

trailing edge of the HSYNC signal.

0x06

R/W

[7:0]

00010100

Clamp duration

Number of clock periods that the CLAMP signal is actively clamping.

0x07

R/W

[7:0]

00100000

HSYNC output

pulse width

Sets the number of pixel clocks that HSOUT remains active.

0x08

R/W

[7:0]

10000000

Red gain

Controls the ADC input range (contrast) of the red channel. Bigger

values result in less contrast.

0x09

R/W

[7:0]

10000000

Green gain

Same function as the red gain bits, but for the green channel.

0x0A

R/W

[7:0]

10000000

Blue gain

Same function as the red gain bits, but for the blue channel.

0x0B

R/W

[7:1]

1000000*

Red offset

Controls dc offset (brightness) of the red channel. Bigger values

decrease brightness.

0x0C

R/W

[7:1]

1000000*

Green offset

Same function as the red offset bits, but for the green channel.

0x0D

R/W

[7:1]

1000000*

Blue offset

Same function as the red offset bits, but for the blue channel.

0x0E

R/W

[7:0]

0*******

Sync control

Bit 7—HSYNC input polarity override. Logic 0 = polarity determined by

chip; Logic 1 = polarity set by Bit 6 in Register 0x0E.

*1******

Bit 6—HSYNC input polarity. Indicates to the PLL the polarity of the

incoming HSYNC signal. Logic 0 = active low; Logic 1 = active high.

**0*****

Bit 5—HSYNC output polarity. Logic 0 = logic high sync; Logic 1 = logic

low sync.

***0****

Bit 4—active HSYNC override. Logic 1 = the user can select the HSYNC

to be used via Bit 3; Logic 0 = the active interface is selected via Bit 6 in

Register 0x14.

****0***

Bit 3—active HSYNC select. Logic 0 = selects HSYNC as the active sync;

Logic 1 = selects sync-on-green as the active sync. Note that the

indicated HSYNC is used only if Bit 4 is set to Logic 1 or if both syncs are

active (Bit 1 and Bit 7 are set to Logic 1 in Register 0x14).

*****0**

Bit 2—VSYNC output invert. Logic 0 = invert; Logic 1 = no invert.

******0*

Bit 1—active VSYNC override. Logic 1 = the user can select the VSYNC to

be used via Bit 0; Logic 0 = the active interface is selected via Bit 3 in

Register 0x14.

*******0

Bit 0—active VSYNC select. Logic 0 = selects raw VSYNC as the output

VSYNC; Logic 1 = selects sync separated VSYNC as the output VSYNC.

Note that the indicated VSYNC is used only if Bit 1 is set to Logic 1.