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PIC16F883 Datasheet(PDF) 30 Page - Microchip Technology |
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PIC16F883 Datasheet(HTML) 30 Page - Microchip Technology |
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30 / 338 page  PIC16F882/883/884/886/887 DS41291G-page 30 2006-2012 Microchip Technology Inc. TABLE 2-3: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 103h STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 000q quuu(3) 104h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 105h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 0000 0000 107h CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 0-00 108h CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 0-00 109h CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — T1GSS C2SYNC 0000 --10 0000 0--0 10Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u 10Ch EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 10Dh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 10Eh EEDATH — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 --00 0000 10Fh EEADRH — — — EEADRH4(2) EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 ---0 0000 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: PIC16F886/PIC16F887 only. 3: See Table 14-5 for Reset value for specific condition. TABLE 2-4: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 183h STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 000q quuu(3) 184h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 185h SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — FVREN 0000 00-0 0000 00-0 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 187h BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 188h ANSEL ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 189h ANSELH — — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 --11 1111 1111 1111 18Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u 18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 ---- q000 18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---- Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: PIC16F884/PIC16F887 only. 3: See Table 14-5 for Reset value for specific condition. |
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