DMOS Dual Full-Bridge

Microstepping PWM Motor Driver

A3992

13

Allegro MicroSystems, LLC

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Package LP, 24 Pin TSSOP with Exposed Thermal Pad

Package LP, 24 Pin TSSOP with Exposed Thermal Pad

1.20 MAX

C

SEATING

PLANE

0.15 MAX

C

0.10

24X

0.65

6.10

3.00

4.32

1.65

0.45

0.65

0.25

2

1

24

3.00

4.32

(1.00)

GAUGE PLANE

SEATING PLANE

B

A

A Terminal #1 mark area

B

For Reference Only

(reference JEDEC MO-153 ADT)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Reference land pattern layout (reference IPC7351

TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all

adjacent pads; adjust as necessary to meet application process

requirements and PCB layout tolerances; when mounting on a multilayer

PCB, thermal vias at the exposed thermal pad land can improve thermal

dissipation (reference EIA/JEDEC Standard JESD51-5)

PCB Layout Reference View

Exposed thermal pad (bottom surface)

C

C

7.80 ±0.10

4.40 ±0.10

6.40 ±0.20

0.60 ±0.15

4° ±4

0.25 +0.05

–0.06

0.15 +0.05

–0.06

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Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

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