AD9517-4ASLASHPCBZ datasheet(25/80 Pages) AD

25 / 80 page

Data Sheet

AD9517-4

Rev. E | Page 25 of 80

–100

–110

–120

–130

–140

–150

–160

100M

10M

100k

10k

100

FREQUENCY (Hz)

Figure 37. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4

–120

–160

–150

–140

–130

100M

10M

100k

10k

FREQUENCY (Hz)

Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO at

1.475 GHz; PFD = 15.36 MHz; LBW = 135 kHz; LVPECL Output = 122.88 MHz

–90

–100

–110

–120

–130

–140

–150

–160

100M

10M

100k

10k

FREQUENCY (Hz)

Figure 39. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 1.556 GHz;

PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz

–120

–160

–150

–140

–130

100M

10M

100k

10k

FREQUENCY (Hz)

Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) at

245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz

1000

100

0.1

0.01

0.1

100

1000

JITTER FREQUENCY (kHz)

OC-48 OBJECTIVE MASK

AD9517

NOTE: 375UI MAX AT 10Hz OFFSET IS THE

MAXIMUM JITTER THAT CAN BE

GENERATED BY THE TEST EQUIPMENT.

FAILURE POINT IS GREATER THAN 375UI.

fOBJ

Figure 41. GR-253 Jitter Tolerance Plot

AD9517-4A/PCBZ Datasheet(PDF) 25 Page - Analog Devices

AD9517-4A/PCBZ Datasheet(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL