MC68HC datasheet(51/124 Pages) FREESCALE

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RESETS AND INTERRUPTS

TECHNICAL DATA

5-7

The maskable interrupt sources have the following priority arrangement:

1. IRQ

2. Real-time interrupt

3. Timer input capture 1

4. Timer input capture 2

5. Timer input capture 3

6. Timer output compare 1

7. Timer output compare 2

8. Timer output compare 3

9. Timer output compare 4

10. Timer input capture 4/output compare 5

11. Timer overflow

12. Pulse accumulator overflow

13. Pulse accumulator input edge

14. SPI transfer complete

15. SCI system

Any one of these interrupts can be assigned the highest maskable interrupt priority by

writing the appropriate value to the PSEL bits in the HPRIO register. Otherwise, the

priority arrangement remains the same. An interrupt that is assigned highest priority is

still subject to global masking by the I bit in the CCR, or by any associated local bits.

Interrupt vectors are not affected by priority assignment. To avoid race conditions,

HPRIO can be written only while I-bit interrupts are inhibited.

5.3.1 Highest Priority Interrupt and Miscellaneous Register

The values of the RBOOT, SMOD, IRVNE, and MDA reset bits depend on the mode

during initialization. Refer to Table 5-3.

RBOOT — Read Bootstrap ROM

Has meaning only when the SMOD bit is a one (special bootstrap mode or special test

mode). At all other times this bit is clear and cannot be written. Refer to SECTION 4

OPERATING MODES AND ON-CHIP MEMORY for more information.

SMOD — Special Mode Select

This bit reflects the inverse of the MODB input pin at the rising edge of reset. Refer to

SECTION 4 OPERATING MODES AND ON-CHIP MEMORY for more information.

MDA — Mode Select A

The mode select A bit reflects the status of the MODA input pin at the rising edge of

reset. Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY for more

information.

IRVNE — Internal Read Visibility Enable/Not E

HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous

$003C

Bit 7

654321

Bit 0

RBOOT

SMOD

MDA

IRVNE

PSEL3

PSEL2

PSEL1

PSEL0

RESET:

—

0101

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