MPC5607B datasheet(38/110 Pages) FREESCALE

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MPC5607B Microcontroller Data Sheet, Rev. 6

Electrical characteristics

Freescale Semiconductor

NOTE

RAM data retention is guaranteed with VDD_LV not below 1.08 V.

VDD_BV

SR Voltage on VDD_BV pin (regulator supply) with

respect to ground (VSS)

—4.5

5.5

Voltage drop2

3.0

5.5

Relative to VDD

3.0

VDD +0.1

VSS_ADC

SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1

(ADC reference) pin with respect to ground (VSS)

—VSS  0.1 VSS +0.1

VDD_ADC

SR Voltage on VDD_HV_ADC0, VDD_HV_ADC1

(ADC reference) with respect to ground (VSS)

—4.5

5.5

Voltage drop2

3.0

5.5

Relative to VDD VDD  0.1 VDD +0.1

VIN

SR Voltage on any GPIO pin with respect to ground

(VSS)

—VSS  0.1

—

Relative to VDD

—VDD +0.1

IINJPAD

SR Injected input current on any pin during overload

condition

—

55

IINJSUM

SR Absolute sum of all injected input currents during

overload condition

—

50

TVDD

SR VDD slope to ensure correct power up

—

0.25

V/µs

TA C-Grade Part SR Ambient temperature under bias

fCPU < 64 MHz

40

°C

TJ C-Grade Part SR Junction temperature under bias

—

40

110

TA V-Grade Part SR Ambient temperature under bias

fCPU < 64 MHz

40

105

TJ V-Grade Part SR Junction temperature under bias

—

40

130

TA M-Grade Part SR Ambient temperature under bias

fCPU < 64 MHz

40

125

TJ M-Grade Part SR Junction temperature under bias

—

40

150

1 100 nF capacitance needs to be provided between each V

DD/VSS pair.

2 Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain

analog electrical characteristics will not be guaranteed to stay within the stated limits.

3 330 nF capacitance needs to be provided between each V

DD_LV/VSS_LV supply pair.

4 470 nF capacitance needs to be provided between V

DD_BV and the nearest VSS_LV (higher value may be needed

depending on external regulator characteristics). While the supply voltage ramps up, the slope on VDD_BV should

be less than 0.9VDD_HV in order to ensure the device does not enter regulator bypass mode.

5 100 nF capacitance needs to be provided between V

DD_ADC/VSS_ADC pair.

6 Guaranteed by device validation. Please refer to Section 4.5.1, “External ballast resistor recommendations for

minimum VDD slope to be guaranteed to ensure correct power up in case of external resistor usage.

7 This frequency includes the 4% frequency modulation guardband.

Table 13. Recommended operating conditions (5.0 V) (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

MPC5607B Datasheet(PDF) 38 Page - Freescale Semiconductor, Inc

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