DAC0832LCWM datasheet(2/29 Pages) TI

2 / 29 page

DAC0830, DAC0832

SNAS534B – MAY 1999 – REVISED MARCH 2013

www.ti.com

Connection Diagrams

(Top Views)

Figure 1. PDIP, CDIP, and SOIC Packages

Figure 2. PLCC Package

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1) (2) (3)

Supply Voltage (VCC)

17 VDC

Voltage at Any Digital Input

VCC to GND

Voltage at VREF Input

±25V

Storage Temperature Range

−65°C to +150°C

Package Dissipation at

500 mW

TA=25°C

(4)

DC Voltage Applied to

−100 mV to VCC

IOUT1 or IOUT2

(5)

ESD Susceptability(5)(6)

800V

Lead

PDIP Package (plastic)

260°C

Temperature

CDIP Package (ceramic)

300°C

(Soldering, 10

SOIC Package

Vapor Phase (60 sec.)

215°C

sec.)

Infrared (15 sec.)

220°C

(1)

All voltages are measured with respect to GND, unless otherwise specified.

(2)

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not

apply when operating the device beyond its specified operating conditions.

(3)

If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

(4)

The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,

TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute

Maximum Ratings, whichever is lower. For this device, TJMAX = 125°C (plastic) or 150°C (ceramic), and the typical junction-to-ambient

thermal resistance of the J package when board mounted is 80°C/W. For the NFH package, this number increases to 100°C/W and for

the FN package this number is 120°C/W.

(5)

For current switching applications, both IOUT1 and IOUT2 must go to ground or the “Virtual Ground” of an operational amplifier. The

linearity error is degraded by approximately VOS ÷ VREF. For example, if VREF = 10V then a 1 mV offset, VOS, on IOUT1 or IOUT2 will

introduce an additional 0.01% linearity error.

(6)

Human body model, 100 pF discharged through a 1.5 k

Ω resistor.

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