RES

SS

LO

HO

5V

t1

Current Limit Detected

at CS

2.5V

0V

+110 PA

+1 PA

t2

t3

#1V

t3 =

110 PA

t2 =

1 PA

LM5035B

SNVS613C – JULY 2009 – REVISED APRIL 2013

www.ti.com

equal to:

(16)

The soft-start time t3 is set by the internal 110 µA current source, and is equal to:

(17)

The time t2 provides a periodic cool-down time for the power converter in the event of a sustained overload or

short circuit. This off time results in lower average input current and lower power dissipation within the power

components. It is recommended that the ratio of t2 / (t1 + t3) be in the range of 5 to 10 to take advantage of this

feature.

If the application requires no delay from the first detection of a current limit condition to the onset of the hiccup

mode (t1 = 0), the RES pin can be left open (no external capacitor). If it is desired to disable the hiccup mode

entirely, the RES pin should be connected to ground (AGND).

Figure 28. Hiccup Over-Load Restart Timing

Printed Circuit Board Layout

The LM5035B Current Sense and PWM comparators are very fast, and respond to short duration noise pulses.

The components at the CS, COMP, SS, OVP, UVLO, DLY and the RT pins should be as physically close as

possible to the IC, thereby minimizing noise pickup on the PC board tracks.

Layout considerations are critical for the current sense filter. If a current sense transformer is used, both leads of

the transformer secondary should be routed to the sense filter components and to the IC pins. The ground side

of the transformer should be connected via a dedicated PC board track to the AGND pin, rather than through the

ground plane.

If the current sense circuit employs a sense resistor in the drive transistor source, low inductance resistors

should be used. In this case, all the noise sensitive, low-current ground tracks should be connected in common

near the IC, and then a single connection made to the power ground (sense resistor ground point).

The gate drive outputs of the LM5035B should have short, direct paths to the power MOSFETs in order to

minimize inductance in the PC board traces. The SR control outputs should also have minimum routing distance

through the pulse transformers and through the secondary gate drivers to the sync FETs.

26

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