TPS51116PWPR datasheet(21/42 Pages) TI1

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ESR +

OUT

0.015

RIPPLE

0.75

[

VOUT

OUT(max)

60 [mW]

(25)

Thermal Design

DSRC + VVLDOIN * VVTT

VTT

(26)

DSNK + VVTT

VTT

(27)

PKG +

J(max) * TA(max)

qJA

(28)

TPS51116

www.ti.com................................................................................................................................................................ SLUS609H – MAY 2004 – REVISED JULY 2009

The external components selection is much simple in D-CAP™ mode.

1. Choose inductor. This section is the same as the current mode. Please refer to the instructions in the

Current Mode Operation section.

2. Choose output capacitor(s).Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are

recommended. Determine ESR to meet required ripple voltage above. A quick approximation is shown in

Equation 25.

Primary power dissipation of TPS51116 is generated from VTT regulator. VTT current flow in both source and

sink directions generate power dissipation from the part. In the source phase, potential difference between

VLDOIN and VTT times VTT current becomes the power dissipation, WDSRC.

In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can be

decreased.

For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, WDSNK,

is calculated by Equation 27:

Since this device does not sink AND source the current at the same time and IVTT varies rapidly with time, actual

power dissipation need to be considered for thermal design is an average of above value. Another power

consumption is the current used for internal control circuitry from V5IN supply and VLDOIN supply. V5IN

supports both the internal circuit and external MOSFETs drive current. The former current is in the VLDOIN

supply can be estimated as 1.5 mA or less at normal operational conditions.

These powers need to be effectively dissipated from the package. Maximum power dissipation allowed to the

package is calculated by Equation 28,

where

• T

J(max) is 125°C

• T

A(max) is the maximum ambient temperature in the system

• θ

JA is the thermal resistance from the silicon junction to the ambient

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