MC68331TS datasheet(62/84 Pages) FREESCALE

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MC68331TS/D

HALT — Halt

0 = Halt not enabled

1 = Halt enabled

When HALT is asserted, the QSPI stops on a queue boundary. It is in a defined state from which it can

later be restarted.

SPSR contains QSPI status information. Only the QSPI can assert the bits in this register. The CPU

reads this register to obtain status information and writes it to clear status flags.

SPIF — QSPI Finished Flag

0 = QSPI not finished

1 = QSPI finished

SPIF is set after execution of the command at the address in ENDQP.

MODF — Mode Fault Flag

0 = Normal operation

1 = Another SPI node requested to become the network SPI master while the QSPI was enabled

in master mode (SS input taken low).

The QSPI asserts MODF when the QSPI is the serial master (MSTR = 1) and the SS input pin is negat-

ed by an external driver.

HALTA — Halt Acknowledge Flag

0 = QSPI not halted

1 = QSPI halted

HALTA is asserted when the QSPI halts in response to CPU assertion of HALT.

Bit 4 — Not Implemented

CPTQP — Completed Queue Pointer

CPTQP points to the last command executed. It is updated when the current command is complete.

When the first command in a queue is executing, CPTQP contains either the reset value ($0) or a point-

er to the last command completed in the previous queue.

5.4.3 QSPI RAM

The QSPI contains an 80-byte block of dual-access static RAM that is used by both the QSPI and the

CPU. The RAM is divided into three segments: receive data, transmit data, and command control data.

Receive data is information received from a serial device external to the MCU. Transmit data is infor-

mation stored by the CPU for transmission to an external peripheral. Command control data is used to

perform the transfer.

Refer to the following illustration of the organization of the RAM.

SPSR — QSPI Status Register

$YFFC1F

SPCR3

SPIF

MODF

HALTA

CPTQP

RESET:

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