MPC5534MVM80 datasheet(2/60 Pages) FREESCALE

2 / 60 page

MPC5534 Microcontroller Data Sheet, Rev. 6

Overview

Freescale Semiconductor

The MPC5500 family of parts contains many new features coupled with high performance CMOS

technology to provide significant performance improvement over the MPC565.

The host processor core of the MPC5534 also includes an instruction set enhancement allowing variable

length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this

enhancement, it is possible to significantly reduce the code size footprint.

The MPC5534 has a single-level memory hierarchy consisting of 64-kilobytes (KB) on-chip SRAM and

one megabyte (MB) of internal flash memory. Both the SRAM and the flash memory can hold instructions

and data. The external bus interface (EBI) supports most standard memories used with the MPC5xx family.

The MPC5534 does not support arbitration with other masters on the external bus. The MPC5534 must be

the only master on the external bus, or act as a slave-only device.

The complex input/output timer functions of the MPC5534 are performed by an enhanced time processor

unit (eTPU) engine. The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over

the TPU by providing: 24-bit timers, double-action hardware channels, variable number of parameters per

channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is

programmed using a high-level programming language.

The less complex timer functions of the MPC5534 are performed by the enhanced modular input/output

system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action,

pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include

edge-aligned and center-aligned PWM.

Off-chip communication is performed by a suite of serial protocols including controller area networks

(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications

interfaces (eSCIs).

The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC) with a 5 V

conversion range. The 324 package has 40-channels; the 208 package has 34 channels.

The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration

and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset

control are also determined by the SIU. The internal multiplexer sub-block (IMUX) provides multiplexing

of eQADC trigger sources and external interrupt signal multiplexing.

MPC5534MVM80 Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc