79C940

Specification Number 79C940B-CI (A) Rev C

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93

AC CHARACTERISTICS (Unless otherwise noted, parametric values are the same

between Commercial devices and Industrial devices.)

Notes:

1. The following BIU timing assumes that EDSEL = 1. Therefore, these parameters are specified with respect to the falling edge

of SCLK (SCLK↓). If EDSEL = 0, the same parameters apply but should be referenced to the rising edge of SCLK ↑).

vs. Load Chart.

3. Guaranteed by design–not tested.

No.

Parameter

Symbol

Parameter Description

Test Conditions

Min (ns)

Max (ns)

Clock and Reset Timing

SCLK period

40

1000

SCLK LOW pulse width

SCLK HIGH pulse width

SCLK rise time

5

SCLK fall time

5

RESET pulse width

Network Bit Time (BT)=2*tX1 or tSTDC

99

101

Internal MENDEC Clock Timing

XTAL1 period

49.995

50.005

11

XTAL1 HIGH pulse width

20

12

XTAL1 LOW pulse width

20

13

XTAL1 rise time

5

14

XTAL1 fall time

5

BIU TIMING (Note 1)

31

Address valid setup to SCLK↓

9

32

Address valid hold after SCLK↓

2

1. 33

CS or FDS and TC, BE1–0,

R/W setup to SCLK↓

9

34

CS or FDS and TC, BE1–0,

R/W hold after SCLK↓

2

35

Data out valid delay from SCLK↓

32

36

Data out valid hold from SCLK↓

6

37

DTV valid delay from SCLK↓

32

38

DTV valid hold after SCLK↓

6

39

EOF valid delay from SCLK↓

32

40

EOF output valid hold after SCLK↓

6

41

CS inactive prior to SCLK↓

9

42

EOF input valid setup to SCLK↓

9

43

EOF input valid hold after SCLK↓

2

44

RDTREQ valid delay from SCLK↓

32

45

RDTREQ input valid hold after SCLK↓

6

46

TDTREQ valid delay from SCLK↓

32

47

TDTREQ input valid hold after SCLK↓

6

48

Data in valid setup to SCLK↓

9

49

Data in valid setup after SCLK↓

2

50

Data output enable delay from SCLK↓ (Note

3)

0

51

Data output disable delay from SCLK↓ (Note

3, 4)

25

TABLE 5

SPECIFICATION NUMBER: 79C940-CI (A) REV -

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