AD9912ABCPZ datasheet(7/40 Pages) AD

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AD9912

Rev. F | Page 7 of 40

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CMOS Output Driver

(AVDD3/Pin 37) @ 1.8 V

Frequency Range

0.008

MHz

See Figure 28 for maximum toggle rate

Duty Cycle

With 20 pF load and up to 40 MHz

Rise Time/Fall Time (20% to 80%)

6.8

With 20 pF load

DAC OUTPUT CHARACTERISTICS

DCO Frequency Range (1st Nyquist Zone)

450

MHz

DAC lower limit is 0 Hz; however, the minimum slew rate

for FDBK_IN dictates the lower limit if using CMOS or HSTL

outputs

Output Resistance

Single-ended (each pin internally terminated to AVSS)

Output Capacitance

Full-Scale Output Current

31.7

Range depends on DAC RSET resistor

Gain Error

−10

+10

% FS

Output Offset

0.6

μA

Voltage Compliance Range

AVSS −

0.50

+0.5

AVSS +

0.50

Outputs connected to a transformer whose center tap is

grounded

Wideband SFDR

See the Typical Performance Characteristics section

20.1 MHz Output

−79

dBc

0 MHz to 500 MHz

98.6 MHz Output

−67

dBc

0 MHz to 500 MHz

201.1 MHz Output

−61

dBc

0 MHz to 500 MHz

398.7 MHz Output

−59

dBc

0 MHz to 500 MHz

Narrow-Band SFDR

See the Typical Performance Characteristics section

20.1 MHz Output

−95

dBc

±250 kHz

98.6 MHz Output

−96

dBc

±250 kHz

201.1 MHz Output

−91

dBc

±250 kHz

398.7 MHz Output

−86

dBc

±250 kHz

DIGITAL TIMING SPECIFICATIONS

Time Required to Enter Power-Down

μs

Time Required to Leave Power-Down

μs

Reset Assert to High-Z Time

for S1 to S4 Configuration Pins

Time from rising edge of RESET to high-Z on the S1, S2, S3,

S4 configuration pins

SERIAL PORT TIMING SPECIFICATIONS

SCLK Clock Rate (1/tCLK )

MHz

Refer to Figure 56 for all write-related serial port parameters;

maximum SCLK rate for readback is governed by tDV

SCLK Pulse Width High, tHIGH

SCLK Pulse Width Low, tLOW

SDO/SDIO to SCLK Setup Time, tDS

1.93

SDO/SDIO to SCLK Hold Time, tDH

1.9

SCLK Falling Edge to Valid Data on

SDIO/SDO, tDV

Refer to Figure 54

CSB to SCLK Setup Time, tS

1.34

CSB to SCLK Hold Time, tH

−0.4

CSB Minimum Pulse Width High, tPWH

IO_UPDATE Pin Setup Time

(from SCLK Rising Edge of the Final Bit)

tCLK

sec

tCLK = period of SCLK in Hz

IO_UPDATE Pin Hold Time

tCLK

sec

tCLK = period of SCLK in Hz

PROPAGATION DELAY

FDBK_IN to HSTL Output Driver

2.8

FDBK_IN to HSTL Output Driver with 2×

Frequency Multiplier Enabled

7.3

FDBK_IN to CMOS Output Driver

8.0

S-divider bypassed

FDBK_IN Through S-Divider to CMOS

Output Driver

8.6

Frequency Tuning Word Update:

IO_UPDATE Pin Rising Edge to DAC

Output

60/fS

fS = system clock frequency in GHz

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