0

10

20

30

40

50

60

70

80

90

100

0

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

I

-OutputCurrent- A

O

V

=7V

IN

V

=14V

IN

V

=21V

IN

V

=28V

IN

0

10

20

30

40

50

60

70

80

90

100

0

0.5

1

1.5

2

2.5

3

I

-OutputCurrent- A

O

V

=7V

IN

V

=14V

IN

V

=21V

IN

V

=28V

IN

0.9985

0.999

0.9995

1

1.0005

1.001

1.0015

1.002

1.0025

1.003

1.0035

1.004

0

0.5

1

1.5

2

2.5

3

3.5

V

=14V

IN

V

=21V

IN

V

=28V

IN

V

=7V

IN

I

-OutputCurrent- A

O

3.28

3.29

3.3

3.31

3.32

3.33

3.34

3.35

3.36

3.37

3.38

0

5

10

15

20

25

30

V -InputVoltage-V

I

I

=0 A

O

I

=1.5 A

O

I

=3 A

O

TPS54331

www.ti.com

SLVS839D

– JULY 2008 – REVISED JANUARY 2012

ELECTROMAGNETIC INTERFERENCE (EMI) CONSIDERATIONS

As EMI becomes a rising concern in more and more applications, the internal design of the TPS54331 takes

measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage

ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used

to lower the parasitics effects.

To achieve the best EMI performance, external component selection and board layout are equally important.

Follow the Step by Step Design Procedure above to prevent potential EMI issues.

APPLICATION CURVES

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Figure 17. TPS54331D Efficiency

Figure 18. TPS54331D Low Current Efficiency

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Figure 19. TPS54331D Load Regulation

Figure 20. TPS54331D Line Regulation

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Copyright

© 2008–2012, Texas Instruments Incorporated

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