| Electronic Components Datasheet Search |
|
MPC8315VRAGDA Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8315VRAGDA Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
|
2 / 106 page ![]() MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor Overview 1 Overview The MPC8315E incorporates the e300c3 (MPC603e-based) core, which includes 16 Kbytes of L1 instruction and data caches, on-chip memory management units (MMUs), and floating-point support. In addition to the e300 core, the SoC platform includes features such as dual enhanced three-speed 10, 100, 1000 Mbps Ethernet controllers (eTSECs) with SGMII support, a 32- or 16-bit DDR1/DDR2 SDRAM memory controller, dual SATA 3 Gbps controllers (MPC8315E-specific), a security engine to accelerate control and data plane security protocols, and a high degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration. The MPC8315E also offers peripheral interfaces such as a 32-bit PCI interface with up to 66 MHz operation, 16-bit enhanced local bus interface with up to 66 MHz operation, TDM interface, and USB 2.0 with an on-chip USB 2.0 PHY. The MPC8315E offers additional high-speed interconnect support with dual integrated SATA 3 Gbps interfaces and dual single-lane PCI Express interfaces. When not used for PCI Express, the SerDes interface may be configured to support SGMII. The MPC8315E security engine (SEC 3.3) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. This figure shows a block diagram of the MPC8315E. Figure 1. MPC8315E Block Diagram 2 MPC8315E Features The following features are supported in the MPC8315E. 2.1 e300 Core The e300 core has the following features: • Operates at up to 400 MHz eTSEC RTBI, SGMII DUART Interrupt I2C Timers GPIO Enhanced DDR1/DDR2 Controller Controller PCI I/O Sequencer (IOS) Security Note: The MPC8315 do not include a security engine. Local Bus, USB 2.0 HS Host/Device/OTG ULPI On-Chip HS PHY SPI Engine 3.3 PCI Express x1 SATA PHY DMA SATA PHY TDM RGMII, (R)MII eTSEC RTBI, SGMII RGMII, (R)MII 16-KB D-Cache 16-KB I-Cache e300c3 Core with Power Management FPU PCI Express x1 MPC8315E |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |