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PowerSSO-36 Datasheet(PDF) 36 Page - STMicroelectronics |
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PowerSSO-36 Datasheet(HTML) 36 Page - STMicroelectronics |
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36 / 53 page ![]() Functional description of the SPI L99H01 36/53 DocID15567 Rev 5 4.4.1 SPI clock monitor and watchdog Figure 11. Global error flag diagram 1. Writing a “1” to RWD - bit in ApplRegx restarts the internal watchdog counter. The clock monitor counts the number of clock pulses during a communication frame (while CSN is low). If the number of SCK pulses does not correspond with the frame width indicated in the <SPI-frame-ID> (ROM address 03hex) the frame is ignored and the bit <frame error> in the <Global Status Byte> is set. Note: Due to this safety functionality, daisy chaining the SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended. |
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