AD650SD datasheet(14/20 Pages) AD

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AD650

Data Sheet

Rev. E | Page 14 of 20

100k

100

10mV

ACTUAL

IDEAL

50ppm

10V

INPUT VOLTAGE

Figure 16. Exaggerated Nonlinearity at 100 kHz Full Scale

10mV

ACTUAL

VOLTAGE TO FREQUENCY

TRANSFER RELATION

IDEAL RELATION

600ppm

10V

INPUT VOLTAGE

600ppm

Figure 17. Exaggerated Nonlinearity at 1 MHz Full Scale

FULL SCALE FREQUENCY (Hz)

100

10k

100k

Figure 18. PSRR vs. Full-Scale Frequency

PSRR

The power supply rejection ratio is a specification of the change

in gain of the AD650 as the power supply voltage is changed.

The PSRR is expressed in units of parts-per-million change of

the gain per percent change of the power supply (ppm/%). For

example, consider a VFC with a 10 V input applied and an

output frequency of exactly 100 kHz when the power supply

potential is ±15 V. Changing the power supply to ±12.5 V is a

5 V change out of 30 V, or 16.7%. If the output frequency changes

to 99.9 kHz, then the gain has changed 0.1% or 1000 ppm. The

PSRR is 1000 ppm divided by 16.7%, which equals 60 ppm/%.

The PSRR of the AD650 is a function of the full-scale operating

frequency. At low full-scale frequencies the PSRR is determined

by the stability of the reference circuits in the device and can be

very effective. At higher frequencies, there are dynamic errors

that become more important than the static reference signals,

and consequently the PSRR is not quite as effective. The values

of PSRR are typically 0 ± 20 ppm/% at 10 kHz full-scale frequency

(RIN = 40 kΩ, COS = 3300 pF). At 100 kHz (RIN = 40 kΩ, COS =

330 pF) the PSRR is typically +80 ± 40 ppm/%, and at 1 MHz

(RIN = 16.9 kΩ, COS = 51 pF) the PSRR is +350 ± 50 ppm/%.

This information is summarized graphically in Figure 18.

OTHER CIRCUIT CONSIDERATIONS

The input amplifier connected to Pin 1, Pin 2, and Pin 3 is not a

standard operational amplifier. Rather, the design has been

optimized for simplicity and high speed. The single largest

difference between this amplifier and a normal op amp is the lack

of an integrator (or level shift) stage. Consequently, the voltage on

the output (Pin 1) must always be more positive than 2 V below the

inputs (Pin 2 and Pin 3). For example, in the F-to-V conversion

mode (Figure 13) the noninverting input of the op amp (Pin 2)

is grounded, which means that the output (Pin 1) is not able to

go below –2 V. Normal operation of the circuit shown in Figure 13

never calls for a negative voltage at the output, but users can

imagine an arrangement calling for a bipolar output voltage (for

example, ±10 V) by connecting an extra resistor from Pin 3 to a

positive voltage. However, this does not work.

Care should be taken under conditions where a high positive

input voltage exists at or before power up. These situations can

cause a latch up at the integrator output (Pin 1). This is a

nondestructive latch and, as such, normal operation can be

restored by cycling the power supply. Latch up can be prevented

by connecting two diodes (for example, 1N914 or 1N4148) as

shown in Figure 11, thereby preventing Pin 1 from swinging

below Pin 2.

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