AD7274 datasheet(7/28 Pages) AD

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AD7273/AD7274

Rev. 0 | Page 7 of 28

TIMING SPECIFICATIONS

VDD = 2.35 V to 3.6 V; VREF = 2.35 to VDD; TA = TMIN to TMAX, unless otherwise noted.1 Guaranteed by characterization. All input signals

are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

Table 4.

Parameter

Limit at TMIN, TMAX

AD7273/AD7274

Unit

Description

fSCLK2

500

kHz min3

MHz max

tCONVERT

14 × tSCLK

AD7274

12 × tSCLK

AD7273

tQUIET

ns min

Minimum quiet time required between bus relinquish and start of

next conversion

ns min

Minimum CS pulse width

ns min

CS to SCLK setup time

t34

ns max

Delay from CS until SDATA three-state disabled

t44

ns max

Data access time after SCLK falling edge

0.4 tSCLK

ns min

SCLK low pulse width

0.4 tSCLK

ns min

SCLK high pulse width

t74

ns min

SCLK to data valid hold time

ns max

SCLK falling edge to SDATA three-state

ns min

SCLK falling edge to SDATA three-state

4.2

ns max

CS rising edge to SDATA three-state

tPOWER-UP5

μs max

Power-up time from full power-down

1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this

value, a digital buffer or latch must be used.

2 Mark/space ratio for the SCLK input is 40/60 to 60/40.

3 Minimum fSCLK at which specifications are guaranteed.

4 The time required for the output to cross the VIH or VIL voltage.

5 See the Power-Up Times section

SCLK

VIH

VIL

SDATA

Figure 2. Access Time After SCLK Falling Edge

SCLK

VIH

VIL

SDATA

Figure 3. Hold Time After SCLK Falling Edge

SCLK

1.4V

SDATA

Figure 4. SCLK Falling Edge SDATA Three-State

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