| Electronic Components Datasheet Search |
|
ADM3311EARSZ Datasheet(PDF) 16 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADM3311EARSZ Datasheet(HTML) 16 Page - Analog Devices |
|
16 / 24 page ![]() ADM3307E/ADM3310E/ADM3311E/ADM3312E/ADM3315E Data Sheet Rev. I | Page 16 of 24 The transmitter outputs and receiver inputs have a similar protection structure. The receiver inputs can also dissipate some of the energy through the internal 5 kΩ (or 22 kΩ for the ADM3310E) resistor to GND as well as through the protection diodes. RIN Rx D1 D2 RECEIVER INPUT Figure 30. Receiver Input Protection Scheme Tx D1 D2 TRANSMITTER OUTPUT Figure 31. Transmitter Output Protection Scheme The ADM3307E protection scheme is slightly different (see Figure 32 and Figure 33). The receiver inputs, transmitter inputs, and transmitter outputs contain two back-to-back high speed clamping diodes. The receiver outputs (CMOS outputs), the SD and EN pins, contain a single reverse biased high speed clamping diode. Under normal operation with maximum CMOS signal levels, the receiver output, SD, and EN protection diodes have no effect because they are reversed biased. If, however, the voltage exceeds about 15 V, reverse breakdown occurs and the voltage is clamped at this level. If the voltage reaches −0.7 V, the diode is forward biased and the voltage is clamped at this level. The receiver inputs can also dissipate some of the energy through the internal 5 kΩ resistor to GND as well as through the protection diodes. RIN D1 D3 D2 RECEIVER INPUT RECEIVER OUTPUT Rx Figure 32. ADM3307E Receiver Input Protection Scheme D1 D2 D3 D4 TRANSMITTER OUTPUT TRANSMITTER INPUT Tx Figure 33. ADM3307E Transmitter Output Protection Scheme The protection structures achieve ESD protection up to ±15 kV on all RS-232 I/O lines (and all CMOS lines, including SD and EN for the ADM3307E). For methods used to test the protection scheme, see the ESD Testing (IEC 1000-4-2) section. ESD TESTING (IEC 1000-4-2) IEC 1000-4-2 (previously 801-2) specifies compliance testing using two coupling methods, contact discharge and air-gap discharge. Contact discharge calls for a direct connection to the unit being tested. Airgap discharge uses a higher test voltage but does not make direct contact with the unit under testing. With air discharge, the discharge gun is moved toward the unit under testing, which develops an arc across the air gap, thus the term air discharge. This method is influenced by humidity, temperature, barometric pressure, distance, and rate of closure of the discharge gun. The contact discharge method, while less realistic, is more repeatable and is gaining acceptance in preference to the air-gap method. Although very little energy is contained within an ESD pulse, the extremely fast rise time coupled with high voltages can cause failures in unprotected semiconductors. Catastrophic destruction can occur immediately as a result of arcing or heating. Even if catastrophic failure does not occur immediately, the device can suffer from parametric degradation that can result in degraded performance. The cumulative effects of continuous exposure can eventually lead to complete failure. I/O lines are particularly vulnerable to ESD damage. Simply touching or plugging in an I/O cable can result in a static discharge that can damage or completely destroy the interface product connected to the I/O port. Traditional ESD test methods, such as the MIL-STD-883B method 3015.7, do not fully test a product’s susceptibility to this type of discharge. This test was intended to test a product’s susceptibility to ESD damage during handling. Each pin is tested with respect to all other pins. There are some important differences between the traditional test and the IEC test. • The IEC test is much more stringent in terms of discharge energy. The peak current injected is over four times greater. • The current rise time is significantly faster in the IEC test. • The IEC test is carried out while power is applied to the device. It is possible that the ESD discharge could induce latch-up in the device under test. This test, therefore, is more representative of a real world I/O discharge where the equipment is operating normally with power applied. For maximum peace of mind, however, both tests should be performed, ensuring maximum protection both during handling and later during field service. |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |