Data Sheet

AD9914

Rev. C | Page 43 of 48

Digital Ramp Rate Register—Address 0x08

This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG)

section for details.

Table 23. Bit Descriptions for Digital Ramp Rate Register

Bit(s)

Mnemonic

Description

[31:16]

Digital ramp negative slope

rate

16-bit digital ramp negative slope value that defines the time interval between decrement

values.

[15:0]

Digital ramp positive slope

rate

16-bit digital ramp positive slope value that defines the time interval between increment

values.

Lower Frequency Jump Register—Address 0x09

This register is effective only if the digital ramp enable bit (0x01[19]) = 1 and the frequency jump enable bit (0x01[14]) = 1 in the CFR2

register. See the Digital Ramp Generator (DRG) section for details.

Table 24. Bit Descriptions for Lower Frequency Jump Register

Bit(s)

Mnemonic

Description

[31:0]

Lower frequency jump

point

32-bit digital lower frequency jump value. Any time the lower frequency jump value is

reached during a frequency sweep, the output frequency jumps to the upper frequency

value instantaneously and continues frequency sweeping in a phase-continuous manner.

Upper Frequency Jump Register—Address 0x0A

This register is effective only if the digital ramp enable bit (0x01[19]) = 1 and the frequency jump enable bit (0x01[14]) = 1 in the CFR2

register. See the Digital Ramp Generator (DRG) section for details.

Table 25. Bit Descriptions for Upper Frequency Jump Register

Bit(s)

Mnemonic

Description

[31:0]

Upper frequency jump

point

32-bit digital upper frequency jump value. Any time the upper frequency jump value is

reached during a frequency sweep, the output frequency jumps to the lower frequency

value instantaneously and continues frequency sweeping in a phase-continuous manner.