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S12CPUV2D Datasheet(PDF) 52 Page - Freescale Semiconductor, Inc |
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S12CPUV2D Datasheet(HTML) 52 Page - Freescale Semiconductor, Inc |
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52 / 126 page  MC9S12DJ64 Device User Guide — V01.17 52 Table 2-1 Signal Properties Pin Name Function1 Pin Name Function2 Pin Name Function3 Pin Name Function4 Powered by Internal Pull Resistor Description CTRL Reset State EXTAL — — — VDDPLL None None Oscillator Pins XTAL — — — RESET — — — VDDR External Reset TEST — — — N.A. Test Input VREGEN — — — VDDX Voltage Regulator Enable Input XFC — — — VDDPLL PLL Loop Filter BKGD TAGHI MODC — VDDR Always Up Up Background Debug, Tag High, Mode Input PAD15 AN15 ETRIG1 — VDDA None None Port AD Input, Analog Input AN7 of ATD1, External Trigger Input of ATD1 PAD[14:08] AN[14:08] — — Port AD Inputs, Analog Inputs AN[6:0] of ATD1 PAD07 AN07 ETRIG0 — Port AD Input, Analog Input AN7 of ATD0, External Trigger Input of ATD0 PAD[06:00] AN[06:00] — — Port AD Inputs, Analog Inputs AN[6:0] of ATD0 PA[7:0] ADDR[15:8]/ DATA[15:8] —— VDDR PUCR/ PUPAE Disabled Port A I/O, Multiplexed Address/Data PB[7:0] ADDR[7:0]/ DATA[7:0] —— PUCR/ PUPBE Port B I/O, Multiplexed Address/Data PE7 NOACC XCLKS — PUCR/ PUPEE Mode depen- dant1 Port E I/O, Access, Clock Select PE6 IPIPE1 MODB — While RESET pin is low: Down Port E I/O, Pipe Status, Mode Input PE5 IPIPE0 MODA — Port E I/O, Pipe Status, Mode Input PE4 ECLK — — PUCR/ PUPEE Mode depen- dant1 Port E I/O, Bus Clock Output PE3 LSTRB TAGLO — Port E I/O, Byte Strobe, Tag Low PE2 R/W — — Port E I/O, R/W in expanded modes PE1 IRQ — — Up Port E Input, Maskable Interrupt PE0 XIRQ — — Port E Input, Non Maskable Interrupt PH7 KWH7 —— PERH/ PPSH Disabled Port H I/O, Interrupt PH6 KWH6 —— Port H I/O, Interrupt PH5 KWH5 —— Port H I/O, Interrupt PH4 KWH4 —— Port H I/O, Interrupt PH3 KWH3 —— Port H I/O, Interrupt PH2 KWH2 —— Port H I/O, Interrupt PH1 KWH1 —— Port H I/O, Interrupt PH0 KWH0 —— Port H I/O, Interrupt |
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