REV. A

AD7899

–14–

MICROPROCESSOR INTERFACING

The high-speed parallel interface of the AD7899 allows easy

interfacing to most DSPs and microprocessors. The AD7899

interface of the AD7899 consists of the data lines (DB0 to DB13),

CS, RD, and BUSY/EOC.

AD7899–ADSP-21xx Interface

Figure 14 shows an interface between the AD7899 and the

ADSP-21xx. The

CONVST signal can be generated by the

ADSP-21xx or from some other external source. Figure 14 shows

the

CS being generated by a combination of the DMS signal and

the address bus of the ADSP-21xx. In this way the AD7899 is

mapped into the data memory space of the ADSP-21xx.

The AD7899 BUSY/

EOC line provides an interrupt to the

ADSP-21xx when the conversion is complete. The conversion

result can then be read from the AD7899 using a read operation.

The AD7899 is read using the following instruction

MR0 = DM(ADC)

where MR0 is the ADSP-21xx MR0 register and ADC is the

AD7899 address.

CS

RD

CONVST

DB0–DB13

AD7899

DT1/F0

IRQn

D8–D21

A0–A13

ADSP-21xx

ADDRESS

DECODE

RD

DMS

BUSY/

EOC

Figure 14. AD7899–ADSP-21xx Interface

AD7899–TMS320C5x Interface

Figure 15 shows an interface between the AD7899 and the

TMS320C5x. As with the previous interfaces, conversion can be

initiated from the TMS320C5x or from an external source and

the processor is interrupted when the conversion sequence is

completed. The

CS signal to the AD7899 derived from the DS

signal and a decode of the address bus. This maps the AD7899

into external data memory. The

RD signal from the TMS320 is

used to enable the ADC data onto the data bus. The AD7899 has

a fast parallel bus so there are no wait state requirements. The

following instruction is used to read the conversion results from

the AD7899:

IN D,ADC

where D is Data Memory address and ADC is the AD7899

address.

CS

RD

BUSY/

EOC

CONVST

DB0–DB13

AD7899

PA0

INTn

D0–D13

DS

A0–A13

TMS320C5x

ADDRESS

DECODE

RD

Figure 15. AD7899–TMS320C5x Interface