ADS62 datasheet(25/49 Pages) TI

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GC5330

GC5337

www.ti.com

SLWS226 B

– DECEMBER 2010 – REVISED JANUARY 2011

Back-end AGC

The beAGC function is available for receive channels from DDUC3 and DDUC2 (DDUC1 and DDUC0 may also

be used for receive

—with the formats as described following—but without the beAGC function). When the

floating-point format is selected (described following), the beAGC is not used. For the fixed-point formats, the

beAGC may be on or off. There are separate beAGC blocks associated with DDUC3 and DDUC2, and each

block can process up to 12 channels. Within a block, there are two sets of control parameters. This provides

support for two different signal types sharing the same DDUC block. Each channel may have a

programmable-gain starting point or a fixed gain, and there is a per-channel flexible gating signal to control

freeze/operate intervals for TDD signal types. The beAGC has approximately a 100 dB dynamic range. The

beAGC algorithm adjusts the gain to drive the median magnitude of gain-loop output data to a target threshold

value. There are four step-sizes used (two for above and two for below the threshold), depending on distance

from the threshold value.

Output formatter

There are three operational modes for the RX BB output formatter: byte mode (B, 9 bits), nibble mode (N, 4 bits),

and serial mode (S, 2 bits). The nibble and serial modes allow multiple BB output rates and the use of fewer pins

on the interface. The GC533x can provide up to three different BB output data rates. Table 7 and Table 8

summarize the different modes and pin assignments for the byte, nibble, and serial modes. As can be seen in

Table 8, there are two data formats supported:

•

Floating point (indicated with an F in the mode label; 14- or 16-bit mantissa, 4-bit exponent)

•

Fixed point without gain word (16- or 18-bit options)

In Table 8, BBOUT[X] is the BBOUT differential pair (assumed positive and negative connections), and BB0,

BB1, and BB2 represent three different RX differential baseband input signals that can be at arbitrary rates.

Figure 13 shows the BB output formats. The maximum-data-rate configurations have the DDR clock out

transitioning synchronously with the data (referred to as DDR Mode 0 in the table). At half the maximum possible

data rate (referred to as DDR Mode 1 in the table) and a quarter of the maximum possible data rate (referred to

as DDR Mode 2 in the table), the DDR clock out transitions in the middle of the data-steady time .

Table 7. RX BB Formatter Modes

Total Number of Interface

Maximum Complex Interface Rate per Channel

MODE

Description

Pins

N is the number of channels

1 interface rate (up to 18 bits)

11 = 9 data + 1 clk + 1 sync

(Clk4/4)/N/2; maximum 125 MSPS total (for all channels)

1BF

1 interface rate (up to 16 bits) + exponent (4

10 = 8 data + 1 clk + 1 sync

(Clk4/4)/N/2; maximum 125 MSPS total (for all channels)

bits)

1 interface rate (16 bits)

6 = 4 data + 1 clk + 1 sync

(Clk4/8)/N; maximum 96.15 (Nibble0), 125 (Nibble1) MSPS total

1NF

1 interface rate (14 bits) + exponent (4 bits)

6 = 4 data + 1 clk + 1 sync

(Clk4/8)/N; maximum 96.15 (Nibble0), 125 (Nibble1) MSPS total

1 interface rate (16 bits)

4 = 2 data + 1 clk + 1 sync

(Clk4/16)/N; maximum 48.07 MSPS total

1SF

1 interface rate (14 bits) + exponent (4 bits)

4 = 2 data + 1 clk + 1 sync

(Clk4/16)/N; maximum 48.07 MSPS total

2 interface rates (16 bits)

12 = 4 data + 1 clk + 1 sync +

(Clk4/8)/N; maximum 221.15 MSPS total

4 data + 1 clk + 1 sync

2NF

2 interface rates (14 bits) + exponent (4 bits)

12 = 4 data + 1 clk + 1 sync +

(Clk4/8)/N; maximum 221.15 MSPS total

4 data + 1 clk + 1 sync

2 interface rates (16 bits)

8 = 2 data + 1 clk + 1 sync +

(Clk4/16)/N; maximum 96.15 MSPS total

2 data + 1 clk + 1 sync

2SF

2 interface rates (14 bits)+ exponent (4 bits)

8 = 2 data + 1 clk + 1 sync +

(Clk4/16)/N; maximum 96.15 MSPS total

2 data + 1 clk + 1 sync

3 interface rates (16 bits)

12 = 2 data + 1 clk + 1 sync +

(Clk4/16)/N; maximum 144.23 MSPS total

2 data + 1 clk + 1 sync +

2 data + 1 clk + 1 sync

3SF

3 interface rates (14 bits)+ exponent (4 bits)

12 = 2 data + 1 clk + 1 sync +

(Clk4/16)/N; maximum 144.23 MSPS total

2 data + 1 clk + 1 sync +

2 data + 1 clk + 1sync

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