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M95080 Datasheet(PDF) 25 Page - STMicroelectronics |
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M95080 Datasheet(HTML) 25 Page - STMicroelectronics |
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25 / 42 page  M95080 M95080-W M95080-R Power-up and delivery state Doc ID 022540 Rev 1 25/42 7 Power-up and delivery state 7.1 Power-up state After power-up, the device is in the following state: ● Standby power mode, ● deselected (after power-up, a falling edge is required on Chip Select (S) before any instructions can be started), ● not in the Hold condition, ● the Write Enable Latch (WEL) is reset to 0, ● Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits). 7.2 Initial delivery state The device is delivered with the memory array set to all 1s (each byte = FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0. |
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