Chapter 1: Cyclone IV Device Datasheet

1–35

Switching Characteristics

May 2013

Altera Corporation

Cyclone IV Device Handbook,

Volume 3

Table 1–42 and Table 1–43 list the IOE programmable delay for Cyclone IV E 1.2 V

core voltage devices.

Table 1–42. IOE Programmable Delay on Column Pins for Cyclone IV E 1.2 V Core Voltage Devices (1), (2)

Parameter

Paths

Affected

Number

of

Setting

Min

Offset

Max Offset

Unit

Fast Corner

Slow Corner

C6

I7

A7

C6

C7

C8

I7

A7

Input delay from pin to

internal cells

Pad to I/O

dataout to

core

7

0

1.314

1.211 1.211 2.177 2.340 2.433 2.388 2.508

ns

Input delay from pin to

input register

Pad to I/O

input register

8

0

1.307

1.203 1.203

2.19

2.387 2.540 2.430 2.545

ns

Delay from output

register to output pin

I/O output

register to

pad

2

0

0.437

0.402 0.402 0.747 0.820 0.880 0.834 0.873

ns

Input delay from

dual-purpose clock pin

to fan-out destinations

Pad to global

clock

network

12

0

0.693

0.665 0.665 1.200 1.379 1.532 1.393 1.441

ns

Notes to Table 1–42:

(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.

(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.

Table 1–43. IOE Programmable Delay on Row Pins for Cyclone IV E 1.2 V Core Voltage Devices (1), (2)

Parameter

Paths

Affected

Number

of

Setting

Min

Offset

Max Offset

Unit

Fast Corner

Slow Corner

C6

I7

A7

C6

C7

C8

I7

A7

Input delay from pin to

internal cells

Pad to I/O

dataout to

core

7

0

1.314

1.209 1.209 2.201 2.386 2.510 2.429 2.548

ns

Input delay from pin to

input register

Pad to I/O

input register

8

0

1.312

1.207 1.207 2.202 2.402 2.558 2.447 2.557

ns

Delay from output

register to output pin

I/O output

register to

pad

2

0

0.458

0.419 0.419 0.783 0.861 0.924 0.875 0.915

ns

Input delay from

dual-purpose clock pin

to fan-out destinations

Pad to global

clock

network

12

0

0.686

0.657 0.657 1.185 1.360 1.506 1.376 1.422

ns

Notes to Table 1–43:

(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.

(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.