IR3897MPBF datasheet(33/47 Pages) IRF

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JANUARY 18, 2013 |DATA SHEET | Rev 3.5

IR3897

4A Highly Integrated SupIRBuck

Single‐Input Voltage, Synchronous Buck Regulator

PD‐97663

computations related to the compensation. The small

signal value may be obtained from the manufacturer’s

datasheets, design tools or SPICE models. Alternatively,

they may also be inferred from measuring the power

stage transfer function of the converter and measuring

the double pole frequency FLC and using equation (17)

to compute the small signal Co.

These result to:

FLC=20.5 kHz

FESR=5.3 MHz

Fs/2=300 kHz

Select crossover frequency F0=120 kHz

Since FLC<F0<Fs/2<FESR, Type III is selected to place the

pole and zeros.

Detailed calculation of compensation Type III:

Desired Phase Boost Θ = 70°

1sin

21.2 KHz

1sin







1sin

680.6 kHz

1sin







Select:

0.5*

10.6 kHz and





0.5*

300 kHz



Select C4 = 2.2nF.

Calculate R3, C3 and C2:

;3.08 Ω

osc

FL C V





Select R3 = 3.01 kΩ:

;

4.9 nF, Select:

10 nF







;

176 pF, Select:

120 pF







Calculate R4, R5 and R6:

;

106 Ω, Select:

100 Ω







;

3.41 kΩ,





Select R5 = 3.32 kΩ:

2.37 kΩ Select:

2.37 kΩ

ref

oref

RR R





Setting the Power Good Threshold

In this design IR3897 is used in normal (non‐tracking,

non‐sequencing) mode, therefore the PGood thresholds are

internally set at 90% and 120% of Vref. At startup as soon as

Vsns voltage reaches 0.9*0.5V=0.45V (Fig. 15), after 1.28ms

delay, PGood signal is asserted. As long as the Vsns voltage

is between the threshold range, Enable is high, and no fault

happens, the PGood remains high.

The following formula can be used to set the threshold.

VoutPGood_Th can be taken as 90% of Vout. Choose R7=3.32KΩ:

*0.9 * 7

(34)

*0.9

82.37

PGood Th

Vref

Vout

Vref







The PGood is an open drain output. Hence, it is necessary to

use a pull up resistor, RPG, from PGood pin to Vcc. The value

of the pull‐up resistor must be chosen such as to limit the

current flowing into the PGood pin to less than 5mA when

the output voltage is not in regulation. A typical value used

is 49.9kΩ.

OVP comparator also uses Vsns signal for over Voltage

dectection.With above values for R7 and R8, OVP trip point

(Vout_OVP) is

*1.2 * ( 7

8) / 8 1.44

(35)

OVP

Vout

Vref





Vref Bypass Capacitor

A minimum value of 100pF bypass capacitor is recommended

to be placed between Vref and Gnd pins.This capacitor should

be placed as close as possible to Vref pin..

IR3897MPBF Datasheet(PDF) 33 Page - International Rectifier

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